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US 12,663,921 B2Granted
Memory devices and systems including hybrid cache, and related methods
AssigneeMicron Technology, Inc.
InventorsKishore K. Muchherla, Ashutosh Malshe, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla
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Abstract
Memory devices are disclosed. A memory device may include hybrid cache including single-level cell (SLC) blocks of memory and non-SLC blocks of memory. The memory device may further include a memory controller configured to disable, based on workload of the hybrid cache, a portion of the hybrid cache such that writes are only directed to another, different portion of the cache. Associated methods and systems are also disclosed.
Claims20
A memory device, comprising:
- hybrid cache including single-level cell (SLC) blocks of memory and non-SLC blocks of memory;
- and
- a memory controller configured to disable, based on workload of the hybrid cache, a portion of the hybrid cache such that writes are only directed to another, different portion of the cache.
A method, comprising:
- writing data in one of a first portion of hybrid cache including single-level cell (SLC) blocks of a memory device or a second portion of the hybrid cache including non-SLC blocks of the memory device;
- and
- disabling, based on an endurance associated with the hybrid cache, the first portion of the hybrid cache or the second portion of the hybrid cache such that data is only written to the other of the first portion or the second portion of the hybrid cache.
A system, comprising:
- a memory device including hybrid cache including:
- first cache including single-level cell (SLC) blocks of memory;
- and
- second cache including non-SLC blocks of memory;
- the memory device configured to disable, based on a workload of the hybrid cache, one of the first cache or the second cache from being written to.
2 more elements
Dependencies are inferred from the claim text.