Input/output capacitance reduction with negative impedance
AssigneeIntel Corporation
InventorsIsaac Abraham, Michael W. Altmann, Jonathan Kolet Gamble, Rodolfo Kiyama Armendariz
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsIsaac Abraham, Michael W. Altmann, Jonathan Kolet Gamble, Rodolfo Kiyama Armendariz
Estimating the term…
Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.
A circuit comprising:
A method comprising:
A circuit comprising:
Dependencies are inferred from the claim text.