US 12,660,715 B2Granted

Methods of forming microelectronic devices

AssigneeMicron Technology, Inc.

InventorsFatma Arzum Simsek-Ege, Kunal R. Parekh

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Abstract

A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.

Claims17

Dependent claims

A method of forming a microelectronic device, comprising:

forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines, wherein forming the microelectronic device structure assembly comprises:
forming a first microelectronic device structure comprising a first base semiconductor structure, the digit lines, the word lines, and access devices of the memory cells coupled to the digit lines and the word lines;
forming contact structures coupled to the digit lines within digit line exit regions neighboring the access devices in a first horizontal direction;
forming additional contact structures coupled to the word lines within word line exit regions neighboring the access devices in a second horizontal direction;
forming further contact structures within socket regions;
after forming the further contact structures, forming storage node devices of the memory cells over and in electrical communication with the access devices of the memory cells;
and
forming routing structures over the storage node devices of the memory cells, at least some of the routing structures coupled to the further contact structures and in electrical communication with the storage node devices;
forming an additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices;
bonding the additional isolation material of the additional microelectronic device structure assembly to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly;
and
electrically connecting the memory cells to at least some of the control logic devices after bonding the additional isolation material to the isolation material.

9 more elements

A method of forming a microelectronic device, comprising:

forming a first semiconductor wafer comprising access devices within array regions, digit lines coupled to the access devices and terminating within digit line exit regions neighboring the array regions, and word lines coupled to the access devices and terminating within word line exit regions neighboring the array regions;
forming digit line contact structures extending through and in contact with the digit lines within the digit line exit regions;
forming word line contact structures extending through and in contact with the word lines within the word line exit regions;
forming capacitors over and in electrical communication with the access devices to form memory cells within the array regions;
forming a second semiconductor wafer comprising control logic devices;
attaching the second semiconductor wafer to the first semiconductor wafer such that at least some of the control logic devices of the second semiconductor wafer are positioned within the array regions of the first semiconductor wafer;
forming additional contact structures over the digit line contact structures and the word line contact structures, some of the additional contact structures in contact with the digit line contact structures, some other of the additional contact structures in contact with the word line contact structures;
and
forming routing structures over the control logic devices and the additional contact structures, the routing structures in electrical communication with the control logic devices and the memory cells.

6 more elements

A method of forming a microelectronic device, comprising:

forming an assembly comprising:
an array of volatile memory cells;
digit lines coupled to the array of volatile memory cells and extending in parallel in a first direction;
digit line contact structures extending through and in contact with the digit lines;
word lines coupled to the array of volatile memory cells and extending in parallel in a second direction orthogonal to the first direction;
word line contact structures extending through and in contact with the word lines;
dielectric oxide material overlying the array of volatile memory cells, the digit lines, and the word lines;
and
forming an additional assembly comprising control logic circuitry and additional dielectric oxide material overlying the control logic circuitry;
bonding the additional dielectric oxide material of the additional assembly to the dielectric oxide material of the assembly to attach the additional assembly to the assembly;
forming contact structures coupled to the digit lines and the word lines after bonding the additional dielectric oxide material of the additional assembly to the dielectric oxide material of the assembly;
and
forming routing structures vertically over and coupled to the contact structures and the control logic circuitry.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/491,694Filed 20 Oct 2023 · division
Priority: 30 Jun 2021
Published: US 2024/0047450 A18 Feb 2024
Granted: 16 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10W 90/00
Package configurations
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10B 12/036
Making the capacitor or connections thereto: the capacitor extending under the transistor
H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line

Family

Application17/364,377Parent of this division · filed 30 Jun 2021
US 2024/0047450 A1Pre-grant publication · published 8 Feb 2024
US 11,842,990 B2Parent of this division
US 2023/0005902 A1Published application
US 12,660,715 B2This patent

From the US filing history. Foreign family members aren’t listed.