Semiconductor devices including bonded semiconductor layers and manufacturing methods of the same

A manufacturing method of a semiconductor device, the method comprising:

• preparing a first semiconductor layer including a wire and an electrical element, wherein a plurality of metal pads is on a surface of the first semiconductor layer;
• and
• stacking and bonding a second semiconductor layer on the surface of the first semiconductor layer,
• wherein the plurality of metal pads includes a first metal pad and a second metal pad,
• wherein the second metal pad is smaller in surface area or diameter on the surface of the first semiconductor layer than the first metal pad,
• wherein the second metal pad is between a first region of the surface of the first semiconductor layer where the first metal pad is and a second region of the surface of the first semiconductor layer where a surface metal density is zero (0), and
• wherein a topological change rate of the surface of the first semiconductor layer is less than or equal to a permissible topology change rate expressed as:
• Permissible Topology Change Rate [%/μm]=(Topology Change Reference [Å/μm])/(Relation between Metal Pad Density and Bonded Surface Erosion Depth [Å/%]);
• or
• Permissible Topology Change Rate [%/pitch]={(Topology Change Reference [Å/μm])/(Relation between Metal Pad Density and Bonded Surface Erosion Depth [Å/%])}*Metal Pad Pitch [μm].

A semiconductor device comprising:

• a silicon interposer;
• a memory that includes a plurality of semiconductor chip dies stacked on the silicon interposer;
• and
• a logic circuit on the silicon interposer, wherein the logic circuit includes a central processing unit or a graphics processing unit,
• wherein at least one of the silicon interposer, the plurality of semiconductor chip dies, or the logic circuit includes a plurality of metal pads on a surface thereof,
• wherein the plurality of metal pads includes a first metal pad and a second metal pad,
• wherein the second metal pad is smaller in surface area or diameter on the surface than the first metal pad,
• wherein the second metal pad is between a first region of the surface where the first metal pad is and a second region of the surface where a surface metal density is zero (0), and
• wherein the semiconductor device further comprises an align key adjacent to the first metal pad on the surface of the at least one of the silicon interposer, the plurality of semiconductor chip dies, or the logic circuit.