Chip stacking structure and manufacturing method thereof, chip package structure, and electronic device

A chip stacking structure, comprising:

• a plurality of chips, sequentially stacked and comprising a first chip and a second chip that are located on a first outermost side and a second outermost side of the plurality of chips, respectively, wherein the first and second outermost sides are located on opposite sides of the plurality of chips and, a passive side of the second chip faces a first outer side of the chip stacking structure, and an active side of the first chip faces a second outer side of the chip stacking structure;
• a first redistribution layer, arranged on a side of an active side of the second chip, wherein the first redistribution layer is in contact with and electrically connected to a corresponding one of the plurality of chips;
• a first dielectric layer;
• and
• a second redistribution layer, arranged on the active side of the first chip, wherein the first dielectric layer is located between the first redistribution layer and the second redistribution layer, and the second redistribution layer is electrically connected to at least the first redistribution layer through a first via hole;
• the chip stacking structure further comprises a third redistribution layer arranged on a side of the first redistribution layer away from one of the plurality of chips that is electrically connected to the first redistribution laver;
• the third redistribution layer is electrically connected to the first redistribution layer, and the second redistribution layer is electrically connected to the third redistribution layer through the first via hole;
• a thickness of a metal line layer in the third redistribution layer is greater than a thickness of a metal line layer in the first redistribution laver;
• and
• the second redistribution layer is electrically connected to the third redistribution layer through the first via hole by the metal line layer in the third redistribution layer being electrically connected to a metal line layer in the second redistribution layer through the first via hole.

A chip stacking structure manufacturing method comprising:

• sequentially stacking a plurality of chips, wherein a first redistribution layer is formed on a side of an active side of each chip, and the first redistribution layer is in contact with and electrically connected to at least a corresponding one of the plurality of chips;
• and the plurality of chips comprise a first chip and a second chip that are respectively located on a first outermost side and a second outermost side of the plurality of chips that are sequentially stacked, the first and second outermost sides being located on opposite sides of the plurality of chips;
• forming a plurality of via holes, and filling the via holes with a conductive material;
• and
• forming a second redistribution layer on a side of a passive side of the first chip or a side of a passive side of the second chip, wherein both the passive side of the first chip and the passive side of the second chip face a first outer side and a second outer side of the plurality of chips that are sequentially stacked, and wherein the second redistribution layer is electrically connected to at least the first redistribution layer through at least one of the via holes;
• the chip stacking structure further comprises a third redistribution layer arranged on a side of the first redistribution layer away from one of the plurality of chips that is electrically connected to the first redistribution layer;
• the third redistribution layer is electrically connected to the first redistribution laver, and the second redistribution layer is electrically connected to the third redistribution layer through the least one of the via holes;
• a thickness of a metal line layer in the third redistribution layer is greater than a thickness of a metal line layer in the first redistribution layer;
• and
• the second redistribution layer is electrically connected to the third redistribution layer through the least one of the via holes by the metal line layer in the third redistribution layer being electrically connected to a metal line layer in the second redistribution layer through the least one of the via holes.