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AssigneeMurata Manufacturing Co., Ltd.
InventorsShishir Ray, Anil Kumar, Sinan Goktepeli, Kouassi Sebastien Kouassi
Estimating the term…
Single-chip solutions and related methods that result in much higher capacitance densities than is achievable with current on-chip solutions and which reduce consumption of planar area of a mounting structure. Embodiments of the present invention use vertical stacking to affix one or more discrete embeddable capacitors to an IC chip superstructure or base structure, and either sequentially or concurrently form electrical connections between the discrete embeddable capacitors and the IC chip. The inventive processes are compatible with CMOS fabrication temperatures for the IC chip while allowing use of capacitors that are fabricated using other processes that may involve much higher temperatures. The inventive processes allow connection of relatively large capacitances (e.g., ˜0.5 μF-1 μF) to an IC chip without increasing the 2-D footprint of the IC chip. Some embodiments include reconfigurable discrete/affixed capacitors and/or discrete/affixed capacitors with through-vias (distinct from capacitor electrode connections) for connecting circuitry.
An integrated circuit chip structure including an integrated circuit chip having a first surface and internal circuitry, and including at least one discrete embeddable capacitor affixed to the first surface and electrically coupled to the internal circuitry, wherein at least one of the at least one discrete embeddable capacitor is internally partitioned into an array of capacitor cells and wherein the internal circuitry of the integrated circuit chip includes at least one of a switch or a fuse coupled to at least two capacitor cells of the array of capacitor cells and configured to electrically connect the at least two capacitor cells.
Dependencies are inferred from the claim text.