Self-aligned gate jumper connecting adjacent gates

A semiconductor structure, the semiconductor structure comprising:

• a plurality of source/drain contacts;
• a dielectric cap located on top of each of the plurality of source/drain contacts and on an upper portion of sidewalls of each of the plurality of source/drain contacts;
• a plurality of gates;
• at least one gate contact connecting to at least one of the plurality of gates;
• and
• at least one gate jumper connecting at least two adjacent gates of the plurality of gates.

A method of forming a gate jumper in a semiconductor structure, the method comprising:

• depositing a first layer of an interlayer dielectric on a plurality of gate structures and a plurality of source/drains in a portion of a semiconductor structure;
• patterning and etching the first layer of the interlayer dielectric above each of the plurality of source/drains;
• depositing and planarizing source/drain metal to form a source/drain contact on each of the plurality of source/drains;
• selectively recessing portions of the first layer of the interlayer dielectric between each of a plurality of source/drain contacts on the plurality of source/drains;
• selectively forming a dielectric cap on exposed top portions of each of the plurality of source/drain contacts;
• depositing and planarizing a second layer of the interlayer dielectric on each of the dielectric caps and the first interlayer dielectric;
• forming holes in the first layer of interlayer dielectric and the second layer of interlayer dielectric for one or more gate contacts and one or more gate jumpers on one or more gate structures using a self-aligning, isotropic etching process, wherein the holes for the one or more gate jumpers is etched over at least one dielectric cap on one source/drain contact of the plurality of source/drain contacts and at least two adjacent gates of a nanosheet transistor;
• forming one or more of gate contacts and gate jumpers by contact metal deposition and planarization;
• and
• forming a plurality of vias, wherein each via contact one of a gate contact of the one or more of the one or more gate contacts and a gate jumper of the one or more gate jumpers.