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US 12,660,271 B2Granted
Method of reducing metal gate resistance for next generation NMOS device application
AssigneeApplied Materials, Inc.
InventorsSrinivas Gandikota, Yixiong Yang, Yongjing Lin, Tuerxun Ailihumaer, Tengzhou Ma, Yuanhua Zheng, Zhihui Liu, Shih Chung Chen, Janardhan Devrajan, Yi Xu, Yu Lei, Mandyam Sriram
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Abstract
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.
Claims14
A method of reducing gate resistance in an NMOS device, the method comprising:
- conformally depositing a metal nitride layer and an amorphous silicon (a-Si) layer on a P-metal layer of a metal gate stack, the metal gate stack comprising the P-metal layer on one or more of an N-metal layer, a high-K dielectric layer, and an interfacial layer on a channel, the metal nitride layer comprising one or more of titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), molybdenum nitride (MoN), or tantalum nitride TaN);
- treating the metal nitride layer with a plasma comprising one or more of argon (Ar), nitrogen (N2), or hydrogen (H2) to reduce nitrogen content in the metal nitride layer and form a reduced metal nitride layer;
- and
- depositing a low resistivity metal fill on the reduced metal nitride layer, the low resistivity metal fill comprising one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and aluminum (Al).
1 more element
Dependencies are inferred from the claim text.