Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates with etch back process

An integrated circuit structure, comprising:

• a first fin;
• a second fin;
• a first gate stack over the first fin;
• a second gate stack over the second fin, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
• and
• a dielectric structure comprising a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions, wherein the third portion has a same composition as the first and second portions.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires;
• a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
• and
• a dielectric structure comprising a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions, wherein the third portion has a same composition as the first and second portions.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first fin;
• a second fin;
• a first gate stack over the first fin;
• a second gate stack over the second fin, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
• and
• a dielectric structure comprising a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions, wherein the third portion has a same composition as the first and second portions.