Method of manufacturing a semiconductor device and a semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBlandine Duriez, Georgios Vellianitis, Gerben Doornbos, Marcus Johannes Henricus Van Dal, Martin Christopher Holland, Timothy Vasen
Life of this patent
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Abstract
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.
Claims20
A semiconductor device comprising:
- a transistor including:
- a channel formed as a part of a semiconductor layer disposed on a dielectric layer;
- a gate dielectric layer disposed over the channel;
- a gate electrode layer including a metal gate electrode layer and disposed over the gate dielectric layer;
- gate sidewall spacers disposed on opposite side faces of the gate electrode layer;
- a source and a drain, each including a source/drain epitaxial layer;
- and
- a source/drain contact disposed over the source/drain epitaxial layer and the gate electrode layer;
- and
- one or more of dummy gate structures disposed around the transistor and on the dielectric layer, wherein:
- a height difference between an uppermost portion of the source/drain epitaxial layer and an uppermost portion of the gate electrode layer is less than 5 nm, and
- each of the one or more of dummy gate structures includes a dummy gate dielectric layer made of a same material as the gate dielectric layer and a dummy metal gate electrode layer made of a same material as the gate electrode layer.
A semiconductor device comprising:
- a thin film transistor including:
- a channel formed as a part of a semiconductor layer disposed on a dielectric layer;
- a gate dielectric layer disposed over the channel;
- a gate electrode layer disposed over the gate dielectric layer;
- sidewall spacers disposed on opposite side faces of the gate electrode layer;
- a source and a drain, each including a source/drain epitaxial layer,
- a source/drain contact disposed over the source/drain epitaxial layer and the gate electrode layer, and
- a ratio of a height of an uppermost portion of the source/drain epitaxial layer to a height of an uppermost portion of the gate electrode layer measured from an upper surface of the semiconductor layer is in a range from 0.90 to 1.10.
A semiconductor device comprising:
- a field effect transistor including:
- a channel made of a semiconductor material;
- a gate dielectric layer disposed over the channel;
- a metal gate electrode layer disposed over the gate dielectric layer;
- gate sidewall spacers disposed on opposite side faces of the metal gate electrode layer;
- a source and a drain, each including a source/drain epitaxial layer;
- a source/drain contact disposed over the source/drain epitaxial layer and the metal gate electrode layer;
- and
- a dummy gate structure including a dummy metal gate electrode,
- wherein a height difference between an uppermost portion of the source/drain epitaxial layer and an uppermost portion of the metal gate electrode layer is less than 5 nm.
Dependencies are inferred from the claim text.