Gated protection device structures for an electrostatic discharge protection circuit

A method comprising:

• forming a first well in a semiconductor substrate, wherein the first well has a first conductivity type;
• forming a second well in the semiconductor substrate, wherein the second well has a second conductivity type opposite from the first conductivity type, and the second well adjoins the first well along an interface;
• forming a first doped region of a first terminal in the first well, wherein the first doped region has the second conductivity type;
• forming a second doped region of a second terminal in the second well, wherein the second doped region has the first conductivity type;
• forming a third doped region that includes a first plurality of sections having the first conductivity type and a second plurality of sections having the second conductivity type, wherein each of the first plurality of sections includes a first portion in the first well and a second portion in the second well, each of the second plurality of sections includes a first portion in the first well and a second portion in the second well, the first plurality of sections and the second plurality of sections alternate with a spaced-apart arrangement in a longitudinal direction along a length of the third doped region, the first well and the second well include adjacent portions that are positioned between the first plurality of sections and the second plurality of sections to provide the spaced-apart arrangement, and the third doped region is configured to be electrically floating;
• and
• forming a third terminal including a gate structure that overlaps with a portion of the second well, wherein the portion of the second well and the gate structure are positioned in a lateral direction between the second doped region and the third doped region.