US 12,660,202 B2 · Circuit and method to enhance efficiency of memory

Abstract

A semiconductor device includes: a memory array; a modulation circuit including a first resistive element, a second resistive element and a third resistive element; a regulator including a transistor; and a controller configured to: determine an operation mode of the memory array; generate a first regulated voltage at a drain terminal of the transistor, wherein the first regulated voltage corresponds to a positive temperature coefficient, a negative temperature coefficient or a zero temperature coefficient according to a first resistance ratio between the first resistive element and the second resistive element and a second resistance ratio between the second resistive element and the third resistive element; provide a first access voltage to the memory array in response to the first regulated voltage corresponding to the positive temperature coefficient; and provide a second access voltage to the memory array in response to the first regulated voltage corresponding to the negative temperature coefficient.

Claims20

Dependent claims

A semiconductor device, comprising:

a memory array comprising memory cells and a driver;
a modulation circuit comprising a first resistive element, a second resistive element and a third resistive element;
a regulator connecting the modulation circuit to the memory array, wherein the regulator comprises a transistor;
and
a controller configured to:
determine an operation mode of the memory array;
cause the regulator to generate a first regulated voltage at a drain terminal of the transistor, wherein the first regulated voltage corresponds to a positive temperature coefficient, a negative temperature coefficient or a zero temperature coefficient according to a first resistance ratio between the first resistive element and the second resistive element and a second resistance ratio between the second resistive element and the third resistive element;
during a read operation, cause the driver to provide a first access voltage to the memory cells in response to the first regulated voltage corresponding to the positive temperature coefficient;
and
during a write operation, cause the driver to provide a second access voltage to the memory cells in response to the first regulated voltage corresponding to the negative temperature coefficient.

7 more elements

A semiconductor device, comprising:

a memory array;
a regulator connected to the memory array;
a modulation circuit comprising a first portion, a second portion connected to the first portion, and an output stage connected to the first portion and the second portion;
and
a controller configured to:
cause the first portion to generate a first current, the first current comprising a first branch current and a second branch current, the first branch current having a first magnitude, the second branch current having a second magnitude, a first resistive element receiving the first branch current, a second resistive element receiving the second branch current, and the second resistive element being a first adjustable resistive element;
cause the second portion to generate a second current, the second current comprising a first branch current and a second branch current, the first branch current of the second current having the first magnitude, the second branch current of the second current having the second magnitude, a third resistive element receiving the second branch current of the second current, the third resistive element being a second adjustable resistive element;
cause the output stage to generate a first output voltage and a second output voltage, the first output voltage corresponding to a positive temperature coefficient, the second output voltage corresponding to a negative temperature coefficient, and the first output voltage and the second output voltage are determined by a first resistance ratio between the first resistive element and the second resistive element and a second resistance ratio between the second resistive element and the third resistive element;
and
access the memory array by a read current or a write current through the regulator based on the first output voltage or the second output voltage.

7 more elements

Dependencies are inferred from the claim text.

Circuit and method to enhance efficiency of memory

Life of this patent

Circuit and method to enhance efficiency of memory

Life of this patent

Abstract

Claims20