Memory system with a plurality of select string lines

A memory system comprising:

• a source line expanding to a first direction and a second direction intersecting with the first direction;
• a string select line provided in j layers (“j” is one or more integer number) and provided in a third direction intersecting the first direction and the second direction with respect to the source line;
• a first word line provided in i layers (“i” is two or more integer number) stacked in the third direction and provided in the third direction with respect to the string select line;
• a second word line provided in i layers, provided in the third direction with respect to the string select line and stacked in the third direction, a position of the second word line provided in i layers in the third direction being the same as the first word line provided in i layers;
• a select gate line provided in 1 layer provided in the third direction with respect to the first word line and the second word line, and divided into 2n (“n” is one or more integer number) in a plane expanding to the first direction and the second direction;
• a plurality of memory pillars having semiconductor layers, provided between the first word line and the second word line, provided between the select gate lines facing each other among the 2n select gate lines, and extended in the third direction;
• and
• a control circuit,
• wherein
• the plurality of memory pillars is electrically connected to the source line,
• each of the plurality of memory pillars has a first string provided in a first side of the memory pillar and a second string provided in a second side of the memory pillar,
• the first string has a first transistor, i first memory cells and j second memory cells,
• the i first memory cells are provided between the first transistor and the second memory cell closest to the first transistor among the j second memory cells,
• the first transistor, the i memory cells, and the j second memory cells are electrically connected in series,
• the first transistor is connected to one of the select gate line among the 2n select gate lines,
• the i first memory cells are electrically connected in series, provided along the third direction, and respectively connected to the first word line provided in i layers,
• the second string has a second transistor, i third memory cells, and j fourth memory cells,
• the i third memory cells are provided between the second transistor and the fourth memory cell closest to the second transistor among the j fourth memory cells,
• the second transistor, the i third memory cells and the j fourth memory cells are electrically connected in series,
• the second transistor is connected to one of the select gate line among the 2n select gate lines,
• the i third memory cells are electrically connected in series, provided along the third direction, and respectively connected to the second word line provided in i layers,
• a position of the #1 first word line among the first word line provided in i layers is the closest to a position of the source line, and a position of the #i first word line is the farthest from the position of the source line,
• a position of the #1 second word line among the second word line provided in i layers is the closest to the position of the source line and a position of the #i second word line is the farthest from the position of the source line,
• the i first memory cells and the i third memory cells share the semiconductor layer, and
• j is no larger than n in the second memory cell and the fourth memory cell.