Memory devices having vertical transistors and fabricating methods thereof
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsChao Sun, Ning Jiang, Wei Liu
Life of this patent
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Abstract
Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a 3D semiconductor device includes: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending in a first lateral direction, wherein each word line is shared by a row of the vertical transistors arranged along the first lateral direction; and a plurality of bit lines each extending in a second lateral direction perpendicular to the first lateral direction; wherein the semiconductor bodies are further arranged along a third lateral direction different from the first lateral direction and the second lateral direction.
Claims20
A semiconductor device, comprising:
- an array of vertical transistors each comprising a semiconductor body extending in a vertical direction;
- a plurality of word lines each extending in a first lateral direction, wherein each word line is shared by a row of the vertical transistors arranged along the first lateral direction;
- and
- a plurality of bit lines each extending in a second lateral direction perpendicular to the first lateral direction;
- and
- a plurality of first and second spacers each extending along the first lateral direction between rows of the vertical transistors;
- wherein the plurality of first and second spacers are alternatively arranged along the second lateral direction, and the semiconductor bodies are further arranged along a third lateral direction different from the first lateral direction and the second lateral direction.
A semiconductor device, comprising:
- an array of vertical transistors each comprising:
- a semiconductor body extending in a vertical direction, and
- a gate structure laterally located on at least one side of the semiconductor body;
- and
- a plurality of first and second spacers each extending along the first lateral direction between rows of the vertical transistors;
- wherein each row of the vertical transistors in a first lateral direction sharing a common word line extending in the first lateral direction comprising a plurality of gate structures of the row of the vertical transistors;
- the plurality of first and second spacers are alternatively arranged along a second lateral direction perpendicular to the first lateral direction;
- and
- the semiconductor bodies are aligned along a third lateral direction having an angle of less than 90 degrees with respect to the first lateral direction.
Dependencies are inferred from the claim text.