Solid-state imaging device with ramp generator circuit

A solid-state imaging device, comprising:

• pixel circuits arranged in pixel columns, wherein for each pixel column, signal outputs of the pixel circuits are connected to a data signal line;
• comparator circuits, wherein each comparator circuit is configured to generate an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input, and wherein each first comparator input is connected to one of the data signal lines;
• a ramp generator circuit including at least one resistor network and buffer circuits;
• and
• at least one reference voltage circuit configured to supply a reference voltage to a voltage tap node of at least one of the resistor networks, wherein
• the ramp generator circuit includes a plurality of resistor networks,
• the ramp generator circuit is configured to switch the voltage tap nodes of one of the resistor networks to the input of one of the buffer circuits, and
• each buffer circuit is configured to pass a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.

A solid-state imaging device, comprising:

• pixel circuits arranged in pixel columns, wherein for each pixel column, signal outputs of the pixel circuits are connected to a data signal line;
• comparator circuits, wherein each comparator circuit is configured to generate an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input, and wherein each first comparator input is connected to one of the data signal lines;
• and
• a ramp generator circuit including at least one resistor network and buffer circuits, wherein the ramp generator circuit is configured to generate a voltage ramp signal based on voltages at voltage tap nodes of the at least one resistor network, wherein
• the ramp generator circuit includes a plurality of resistor networks, and wherein the ramp generator circuit is configured to switch the voltage tap nodes of one of the resistor networks to the input of one of the buffer circuit, and
• each buffer circuit is configured to pass a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.