Low latency reset synchronizer circuit

A physical layer within a communications network, comprising:

• a first data communications channel having a first serializer circuit with an input coupled to a first data bus and an output coupled to a first serial data line;
• a second data communications channel having a second serializer circuit with an input coupled to a second data bus and an output coupled to a second serial data line;
• a first reset synchronization circuit configured to receive a reset signal and a clock signal and having an output configured to generate a first reset control signal applied for controlling resetting of the first serializer circuit;
• and
• a second reset synchronization circuit configured to receive said reset signal and said clock signal and having an output configured to generate a second reset control signal applied for controlling resetting of the second serializer circuit;
• wherein each of the first and second reset synchronization circuits comprises:
• a first latching circuit having a reset function controlled by said reset signal and configured to latch a logic state in response to a first edge of said clock signal to generate a first output signal;
• a second latching circuit having a reset function controlled by said reset signal and configured to latch a logic state in response to a second edge of said clock signal to generate a second output signal;
• wherein the first and second edges are opposite edges;
• a combinatorial logic circuit configured to logically combine the first and second output signals to generate a logic output signal;
• and
• a third latching circuit having a reset function controlled by said reset signal and configured to latch the logic output signal in response to said second edge of said clock signal to generate the corresponding one of the first and second reset control signals.

A reset synchronization method, comprising:

• resetting a first latching circuit in response to a reset signal;
• latching by the first latching circuit a logic state in response to a first edge of a clock signal;
• resetting a second latching circuit in response to the reset signal;
• latching by the second latching circuit a logic state in response to a second edge of the clock signal;
• wherein the first and second edges are opposite edges;
• logically combining an output of the first latching circuit with an output of the second latching circuit to generate a logic output signal;
• resetting a third latching circuit in response to the reset signal;
• and
• latching by the third latching circuit the logic output signal in response to the second edge of the clock signal to generate a reset synchronization control signal.