N:1 mux driver for ultra-high speed transmitter
AssigneeCiena Corporation
InventorsNaim Ben Hamida, Faisal Ahmed Musa, Ahmed Mustafa, Mouna Safi-Harab
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Abstract
Aspects of the subject disclosure may include, for example, N-to-1 multiplexers and pulse generators that include NOR logic. The NOR logic pulse generators may include parallel transistors responsive to data and clock signals to pull down an output node when any of the data or clock signals are asserted. The NOR logic pulse generator may also include a pullup structure that includes no more than one active device channel in series between a supply node and the output node. Other embodiments are disclosed.
Claims20
A device comprising:
- a first NOR logic pulse generator that includes:
- a plurality of transistors having drain nodes coupled in parallel to an output node, having source nodes coupled in parallel to a first supply node, and having gate nodes coupled to separate data and clock nodes;
- and
- a pullup structure coupled between the output node and a second supply node, wherein the pullup structure is configured to pull up the output node when all of the plurality of transistors are off, and wherein the pullup structure comprises an active inductor device.
An N-to-1 multiplexer device, comprising:
- a plurality of NOR logic pulse generators, wherein each of the plurality of NOR logic pulse generators includes:
- a plurality of transistors having drain nodes coupled in parallel to an output node, having source nodes coupled in parallel to a first supply node, and having gate nodes coupled to separate data and clock nodes;
- and
- a pullup structure including at least one transistor coupled to form a current path that includes no more than one active device channel in series between a second supply node and the output node;
- and
- a driver circuit that includes a plurality of driver transistors, wherein each of the driver transistors includes a gate node coupled to the output node of a corresponding one of the plurality of NOR logic pulse generators, and wherein the plurality of driver transistors include drain nodes coupled in parallel to sum output signals from the plurality of NOR logic pulse generators, and wherein the N-to-1 multiplexer device includes differential outputs, and wherein a number of NOR logic pulse generators in the N-to-1 multiplexer device is equal to 2N.
A method, comprising:
- providing a plurality of transistors having drain nodes coupled in parallel to an output node, having source nodes coupled in parallel to a first supply node, and having gate nodes coupled to separate data and clock nodes;
- and
- providing a pullup structure including at least one transistor coupled to form a current path that includes no more than one active device channel in series between a second supply node and the output node, wherein the plurality of transistors and the pullup structure form a NOR logic pulse generator that pulls down the output node when any of the plurality of transistors are on and pulls up the output node when all of the plurality of transistors are off, and wherein the pullup structure comprises an active inductor device.
Dependencies are inferred from the claim text.