Clock receiver circuit with rapid clock signal settling

A method, comprising:

• generating an amplified clock signal based on an input clock signal received from a clock generator circuit;
• filtering duty cycle distortion in the amplified clock signal and generating a filtered clock signal;
• generating a control signal after a period of time, wherein the filtered clock signal settles to a clock voltage during the period of time;
• and
• providing the filtered clock signal to one or more other devices based on the control signal.

An apparatus, comprising:

• a clock generator circuit of a first integrated circuit device configured to generate a clock signal for a second integrated circuit device;
• and
• a clock receiver circuit of the second integrated circuit device that receives the clock signal, the clock receiver circuit including:
• an amplification circuit configured to generate an amplified clock signal based on the clock signal received from the clock generator circuit;
• a filter circuit configured to filter duty cycle distortion in the amplified clock signal and generate a filtered clock signal;
• a control circuit configured to generate a first control signal after a period of time, wherein the filtered clock signal settles to a clock voltage during the period of time;
• and
• a gating circuit configured to provide the filtered clock signal to one or more circuits of an integrated circuit device based on the first control signal.