High precision on-chip RC oscillator

An on-chip ULP RC oscillator, the on-chip ULP RC oscillator comprising:

• a first comparator, wherein the first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit, the first bias voltage generation circuit being configured to generate a first bias voltage, and the first capacitor circuit being configured to generate a first proportional to absolute temperature (PTAT) voltage, wherein the first comparator is configured to compare the first bias voltage and the first PTAT voltage, and to generate a first comparator output signal based on the comparison;
• a second comparator, wherein the second comparator comprises a first input electrically coupled to a second bias voltage generation circuit and a second input electrically coupled to a second capacitor circuit, the second bias voltage generation circuit being configured to generate a second bias voltage, and the second capacitor circuit being configured to generate a second PTAT voltage, wherein the second comparator is configured to compare the second bias voltage and the second PTAT voltage and to generate a second comparator output signal based on the comparison, wherein each of the first bias voltage and the second bias voltage directly varies with a thermal voltage;
• and
• a flip-flop electrically coupled to the first comparator and the second comparator, wherein:
• the flip-flop is configured to generate a clock signal based on the first and the second comparator output signals,
• the first and the second bias voltage generation circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series with a resistor, the PTAT current source being configured to produce a current and provide the current to the resistor,
• the PTAT current source comprises a plurality of PMOS transistors and a plurality of NMOS transistors,
• the current is characterized by nVt ln(M)/RB, and
• Vt is the thermal voltage, M is a beta parameter of one of the plurality of PMOS transistors, RB is a bias resistance, and n is a scaling factor.

An on-chip (ULP) RC oscillator, the on-chip ULP RC oscillator comprising:

• a first comparator, wherein the first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit, the first bias voltage generation circuit being configured to generate a first bias voltage, and the first capacitor circuit being configured to generate a first proportional to absolute temperature (PTAT) voltage, wherein the first comparator is configured to compare the first bias voltage and the first PTAT voltage, and to generate a first comparator output signal based on the comparison;
• a second comparator, wherein the second comparator comprises a first input electrically coupled to a second bias voltage generation circuit and a second input electrically coupled to a second capacitor circuit, the second bias voltage generation circuit being configured to generate a second bias voltage, and the second capacitor circuit being configured to generate a second PTAT voltage, wherein the second comparator is configured to compare the second bias voltage and the second PTAT voltage and to generate a second comparator output signal based on the comparison, wherein each of the first bias voltage and the second bias voltage directly varies with a thermal voltage;
• and
• a flip-flop electrically coupled to the first comparator and the second comparator,
• wherein:
• the flip-flop is configured to generate a clock signal based on the first and the second comparator output signals,
• the first and the second capacitor circuits each comprise a proportional to absolute temperature (PTAT) current source electrically coupled in series to an NMOS transistor, a capacitor, and a temperature compensation circuit,
• the PTAT current source is configured to produce a current and provide the current to the NMOS transistor and the capacitor,
• the temperature compensation circuit comprises a second order current source, and
• the second order current source is configured to produce an additional current and provide the additional current to the NMOS transistor and the capacitor.

A method of generating a clock signal, the method comprising:

• generating, by a first bias voltage generation circuit, a first bias voltage;
• generating, by a second bias voltage generation circuit, a second bias voltage;
• generating, by a first capacitor circuit, a first proportional to absolute temperature (PTAT) voltage;
• generating, by a second capacitor circuit, a second PTAT voltage;
• comparing, by a first comparator, the first bias voltage and the first PTAT voltage;
• generating, by the first comparator, a first comparator output signal based on the comparison of the first bias voltage and the first PTAT voltage;
• comparing, by a second comparator, the second bias voltage and the second PTAT voltage;
• generating, by the second comparator, a second comparator output signal based on the comparison of the second bias voltage and the second PTAT voltage, wherein each of the first bias voltage and the second bias voltage directly varies with a thermal voltage;
• generating, by an RS flip-flop electrically coupled to the first comparator and the second comparator, a clock signal based on the first and the second comparator output signals;
• receiving, by a first input of the RS flip-flop, the first comparator output signal;
• receiving, by a second input of the RS flip-flop, the second comparator output signal;
• providing, by a first output of the RS flip-flop, a first offset correction to the first comparator;
• and
• providing, by a second output of the RS flip-flop, a second offset correction to the second comparator.