Memory system with redundant operation

A memory system comprising:

• a memory including an array of memory storage units, read circuitry for providing digital outputs of data stored in the array, and a memory data output for providing digital data read by the read circuitry from the array at an addressable memory location, the memory data output being of a first bit width;
• a system data output for providing data from an addressable memory location of the array indicated by an address received at a system address input, the system data output being of a second bit width less than the first bit width;
• a built-in self-test circuit including a data input to receive data from the memory data output, the data input of the built-in self-test circuit having the first bit width, wherein the built-in self-test circuit is operably coupled to the memory to perform test operations on the memory to determine defective storage units of the memory;
• a system data input to receive data to be written to the array at an addressable memory location indicated by an address received at the system address input, the system data input being of the second bit width;
• wherein the memory includes a memory data input for receiving data to be written to the array at an addressable memory location, the memory data input being of the first bit width;
• data line redirection circuitry for selectively redirecting at least one data line of the system data input from a corresponding data terminal of the memory data input based upon an indication of a determination by the built-in self-test circuit that a storage unit of the memory is defective.

A method of operating a memory system comprising:

• performing memory test operations comprising:
• writing by a built-in self-test circuit, data having a first bit width to a memory of a memory system, the memory receiving the data at a memory data input of the memory having the first bit width;
• reading by the built-in self-test circuit, data having the first bit width from a memory data output of the memory, the memory data output being of the first bit width, the memory data output providing digital data;
• wherein the memory system has a system data input and a system data output having a second bit width that is less than the first bit width.

A memory system comprising:

• a memory including an array of memory storage units, read circuitry for providing digital outputs of data stored in the array, and a memory data output for providing digital data read by the read circuitry from the array at an addressable memory location, the memory data output being of a first bit width;
• a system data output for providing data from an addressable memory location of the array indicated by an address received at a system address input, the system data output being of a second bit width less than the first bit width;
• a system data input to receive data to be written to the array at an addressable memory location indicated by an address received at the system address input, the system data input being of the second bit width, wherein the memory including a memory data input for receiving data to be written to the array at an addressable memory location including data received from the system data input, the memory data input being of the first bit width;
• a built-in self-test circuit including a data input to receive data having the first bit width from the memory data output, the data input of the built-in self-test circuit having the first bit width, the built-in self-test circuit including a data output to provide data to the memory data input to write to the array, wherein the built-in self-test circuit is operably coupled to the memory to perform test operations on the memory to determine defective storage units of the array;
• data line redirection circuitry configurable to provide data received from the system data input to terminals of the memory data input wherein terminals of the memory data input associated with defective storage units of the array as determined by the built-in self-test circuit are not provided data received from the system data input, and configurable to provide data provided to the system data output from terminals of the memory data output wherein data from terminals of the memory data output associated with defective storage units of the array determined by the built-in self-test circuit are not provided to the system data output.