Semiconductor memory device with processing-in-memory using test circuitry

A system-in-package (SiP) device, comprising:

• an interposer substrate;
• a host device carried by the interposer substrate;
• and
• a high bandwidth memory (HBM) device carried by the interposer substrate, wherein the HBM device is coupled to the host device by an interposer bus, and wherein the HBM device comprises:
• an interface die carried by the interposer substrate, the interface die comprising a memory built-in self-test (mBIST) circuit;
• and
• a plurality of memory dies carried by the interface die, wherein the plurality of memory dies is communicably coupled to the interface die,
• wherein the mBIST circuit is configured to:
• detect a command, received over the interposer bus from the host device, to perform a processing-in-memory (PIM) operation;
• read data, from one of the plurality of memory dies, in response to the detected command;
• configure a processing unit (PU) of the HBM device to perform an arithmetic or logical operation on the read data to generate a result;
• and
• write the result data to one of the plurality of memory dies.

A method comprising:

• receiving, at a memory device, a request to perform a multiply-accumulate (MAC) operation on data stored in the memory device;
• generating, at a memory built-in self-test (mBIST) automatic pattern generator (APG) of the memory device, a command to read the data stored in the memory device;
• generating, at the mBIST APG, a command for a processing unit (PU) of the memory device to perform a MAC operation on the read data;
• and
• generating, at the mBIST APG, a command to write result data generated by the PU operation to a memory location of the memory device.