Parallel operations in compute systems

A method for performing a write operation in a compute-in-memory (CIM) macro comprising a column cell having a first set of bitcells connected to a first set of wordlines and a second set of bitcells connected to a second set of wordlines, the method comprising:

• generating, by a weight address decoder, a first set of wordline signals for the first set of wordlines and a second set of wordline signals for the second set of wordlines based on a weight select signal;
• providing a weight value to a set of bitlines shared by the first set of bitcells and the second set of bitcells;
• and
• providing an inverted weight select signal to a set of weight output multiplexers, wherein the set of weight output multiplexers is configured to select first outputs of the first set of bitcells or second outputs of the second set of bitcells.

A system comprising:

• a computing device configured to store an array of weight values and perform a vector matrix multiplication (VMM) operation using the array of weight values,
• the computing device comprising:
• a column cell comprising a first set of bitcells configured to store a first weight value and a second set of bitcells configured to store a second weight value;
• a first set of wordlines and a second set of wordlines configured to address the first set of bitcells and the second set of bitcells, respectively,
• wherein the computing device is configured to perform parallel write operations to the first set of bitcells and the VMM operation in the second set of bitcells based on a weight select signal.