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US 12,658,270 B2Granted
Semiconductor package for performing training operation
AssigneeSK hynix Inc.
InventorsSeong Ju Lee, Yong Sun Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a first memory device configured to output master data after the start of a training operation, and a second memory device configured to sample internal data based on the master data after the start of the training operation, configured to store test codes that adjust a time point at which the internal data are output when a time point at which the master data are output and the time point at which the internal data are output become identical with each other, and configured to program the stored test codes when the training operation is terminated.
Claims15
A semiconductor package comprising:
- a first memory device configured to output master data after a start of a training operation;
- and
- a second memory device configured to sample internal data based on the master data after the start of the training operation, configured to store test codes that adjust a time point at which the internal data are output when a time point at which the master data are output and a time point at which the internal data are output become identical, and configured to program the stored test codes when the training operation is terminated, wherein the second memory device comprises:
- a first clock generation circuit configured to generate a second internal clock having a delay that is adjusted based on a combination of logic levels of the test codes after the start of the training operation, configured to store the test codes when a test latch signal is enabled, and configured to program the stored test codes when the training operation is terminated;
- a second core circuit configured to output the internal data in synchronization with the second internal clock when chip IDs having an identical logic level combination are input after the start of the training operation;
- a first slave receiver configured to generate transfer master data by receiving the master data from the first memory device and configured to output the transfer master data;
- a first slave transmitter configured to receive the internal data from the second core circuit and configured to output the received internal data;
- a second slave receiver configured to generate transfer internal data by receiving the internal data from the first slave transmitter and configured to output the transfer internal data;
- and
- a comparison circuit configured to generate the test latch signal by comparing a time point at which the transfer master data are input to a time point at which the transfer internal data are input,
- wherein the first memory device and the second memory device are simultaneously enabled after the start of the training operation.
8 more elements
A semiconductor package comprising:
- a first memory device configured to sample first internal data based on master data after a start of a training operation and configured to program, in multiple electrical fuses, test codes that adjust a time point at which the first internal data are output when a time point at which the master data are output and a time point at which the first internal data are output become identical;
- and
- a second memory device configured to sample second internal data based on the master data after the start of the training operation and configured to program, in multiple electrical fuses, test codes that adjust a time point at which the second internal data are output when a time point at which the master data are output and a time point at which the second internal data are output become identical,
- wherein the first memory device and the second memory device are simultaneously enabled after the start of the training operation, and
- wherein the first memory device comprises:
- a first input/output control circuit configured to generate a first slave transmission control signal and first and second slave reception control signals that are enabled based on an input chip ID having a first logic level combination after a start of a normal operation;
- a first clock generation circuit configured to generate a first internal clock having a delay that is adjusted based on a combination of logic levels of the test codes after the start of the training operation, configured to store the test code when a first test latch signal is enabled, and configured to program the stored test codes when the training operation is terminated;
- a first core circuit configured to output the first internal data in synchronization with the first internal clock when a chip ID having a second logic level combination is input;
- a first slave receiver configured to generate first transfer master data by receiving the master data when the first slave reception control signal is enabled and configured to output the first transfer master data;
- a first slave transmitter configured to receive the first internal data from the first core circuit when the first slave transmission control signal is enabled and configured to output the received first internal data;
- a second slave receiver configured to generate first transfer internal data by receiving the first internal data from first slave transmitter when the second slave reception control signal is enabled and configured to output the first transfer internal data;
- and
- a first comparison circuit configured to generate the first test latch signal by comparing a time point at which the first transfer master data are input to a time point at which the first transfer internal data are input.
10 more elements
Dependencies are inferred from the claim text.