Nonvolatile memory device and method of operating a nonvolatile memory device

A nonvolatile memory device comprising:

• a memory cell array including a plurality of memory blocks, each memory block of the plurality of memory blocks including a plurality of cell strings, each cell string of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor which are connected in series and arranged in a vertical direction between each bit-line of a plurality of bit-lines and a common source line;
• and
• a control circuit configured to control an erase operation on a target memory block of the plurality of memory blocks, wherein controlling the erase operation on the target memory block comprises:
• determining, based on an erase command and a block address, whether the target memory block is an open block including at least one erased word-line or a closed block consisting of a plurality of programmed word-lines, wherein the block address designates the target memory block from the plurality of memory block;
• based on determining that the target memory block is the closed block consisting of the plurality of programmed word-lines, applying a first pre-program voltage to the plurality of programmed word-lines of the target memory block during pre-program period of an erase loop, the first pre-program voltage having a first voltage level;
• or
• based on determining that the target memory block is the open block including the at least one erased word-line, applying a second pre-program voltage to a portion of a region of the target memory block during the pre-program period, the second pre-program voltage having a second voltage level greater than the first voltage level, wherein the portion of the region of the target memory block includes the at least one erased word-line.

A nonvolatile memory device comprising:

• a memory cell array including a plurality of memory blocks, each memory block of the plurality of memory blocks including a plurality of cell strings, each cell string of the plurality of cell strings including a string selection transistor, a plurality of memory cells, and a ground selection transistor which are connected in series and arranged in a vertical direction between each bit-line of a plurality of bit-lines and a common source line;
• a control circuit configured to control an erase operation on a target memory block of the plurality of memory blocks, wherein controlling the erase operation on the target memory block comprises:
• determining, based on an erase command and a block address, whether the target memory block is an open block including at least one erased word-line or a closed block consisting of a plurality of programmed word-lines, the block address designating the target memory block from the plurality of memory block;
• based on determining that the target memory block is the closed block consisting of the plurality of programmed word-lines, applying a first pre-program voltage to the plurality of programmed word-lines of the target memory block during pre-program period of an erase loop, the first pre-program voltage having a first voltage level;
• and
• based on determining that the target memory block is the open block including the at least one erased word-line, applying a second pre-program voltage to a portion of a region of the target memory block during the pre-program period, the second pre-program voltage having a second voltage level greater than the first voltage level, and the portion of the region of the target memory block including the at least one erased word-line;
• a voltage generator configured to generate, based on a plurality of control signals, a plurality of word-line voltages, the plurality of word-line voltages including the first pre-program voltage, the second pre-program voltage, and an erase voltage;
• and
• an address decoder configured to provide, based on a row address, the plurality of word-line voltages to the target memory block, and
• wherein the control circuit is configured to return the second voltage level of the second pre-program voltage to the first voltage level after an erase operation on the open block is completed.