Sensing circuit in a vertical memory system

A method, comprising:

• applying a first bias voltage, using a first transistor, to a digit line that is coupled with a memory cell and coupled with a gate terminal of a second transistor, wherein a voltage of the digit line increases or decreases to a threshold value based at least in part on applying the first bias voltage;
• removing the first bias voltage from the digit line based at least in part on applying the first bias voltage, wherein the voltage of the digit line after removing voltage of the first bias voltage is based at least in part on a logic state stored by the memory cell;
• applying a second bias voltage to a first terminal of the second transistor based at least in part on removing the first bias voltage from the digit line;
• and
• inverting a voltage of a data node coupled with a third terminal of the second transistor to generate, at an output node, an output voltage representative of the logic state stored by the memory cell, the voltage of the data node based at least in part on the voltage of the digit line.

An apparatus, comprising:

• a memory cell coupled with a word line and a first pillar;
• a first transistor comprising a first terminal coupled with the memory cell through the first pillar, and comprising a second terminal coupled with a digit line, the first transistor physically between a second transistor and a third transistor;
• the second transistor comprising a first terminal coupled with a first bias line and coupled with a second pillar, and comprising a second terminal coupled with the digit line;
• and
• the third transistor comprising a first terminal coupled with a second bias line and coupled with a third pillar, and comprising a gate terminal coupled with the digit line.