Technologies for dynamic biasing for memory cells
AssigneeIntel Corporation
InventorsYasir Mohsin Husain, Xuming Zhao
Life of this patent
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Abstract
In the illustrative embodiment, a source follower sets a voltage on a wordline of a memory cell. A bias voltage on the gate of the source follower can be temporarily increased in order to charge the wordline more quickly. In some embodiments, for a read operation, after a demarcation voltage has been applied to the memory cell for the memory cell to change its resistance if it is set, the bias voltage on the gate of the source follower is decreased in order to prevent the memory cell from changing its resistance while the current through the memory cell is being read. In some embodiments, a current mirror can be activated in order to bleed off charge from the wordline to lower the voltage more quickly.
Claims16
An apparatus for dynamic biasing of memory cells, the apparatus comprising:
- a plurality of three-dimensional crosspoint memory cells;
- and
- control circuitry to:
- receive a memory operation for a memory cell of the plurality of three-dimensional crosspoint memory cells;
- provide, during the memory operation, a first gate bias signal for a source follower for a first amount of time;
- and
- provide, during the memory operation, a second gate bias signal for the source follower for a second amount of time, wherein the second gate bias signal is different from the first gate bias signal and the second amount of time is different from the first amount of time,
- wherein the first gate bias signal biases the source follower in an active region of the source follower, wherein the second gate bias signal biases the source follower in the active region of the source follower.
An apparatus comprising:
- a memory die comprising:
- a plurality of three-dimensional crosspoint memory cells;
- a wordline connected to the plurality of three-dimensional crosspoint memory cells;
- and
- a current mirror connected to the wordline to bleed charge from the wordline to reduce a voltage across a memory cell of the plurality of three-dimensional crosspoint memory cells during a memory operation;
- and
- control circuitry to:
- receive the memory operation for the memory cell of the plurality of three-dimensional crosspoint memory cells;
- provide, during the memory operation, a first gate bias signal for a source follower to charge the wordline;
- provide, during the memory operation, a signal to the current mirror to bleed charge from the wordline;
- and
- provide, during the memory operation, a second gate bias signal for the source follower lower than the first gate bias signal while the current mirror is to bleed charge from the wordline,
- wherein to provide the first gate bias signal comprises to provide a first set of one or more digital inputs to a capacitive digital-to-analog converter.
A method comprising:
- receiving, by control circuitry, a memory operation to be performed on a memory cell of a plurality of three-dimensional crosspoint memory cells;
- providing, during the memory operation and by the control circuitry, a first gate bias signal for a source follower connected to a wordline of the memory cell for a first amount of time;
- and
- providing, during the memory operation and by the control circuitry, a second gate bias signal for the source follower for a second amount of time, wherein the second gate bias signal is different from the first gate bias signal and the second amount of time is different from the first amount of time,
- wherein the first gate bias signal biases the source follower in an active region of the source follower, wherein the second gate bias signal biases the source follower in the active region of the source follower.
Dependencies are inferred from the claim text.