Circuit for non-destructive reading of ferroelectric memories

A data storage circuit comprising:

• a matrix of memory cells such that each memory cell (CMij) comprises:
• an elementary storage component (NVM) of ferroelectric type with variable electric polarisation and having a first electrode (EL1) and a second electrode (EL2);
• a first input/output node (SL) connected to the second electrode (EL2);
• a second input/output node (BL);
• a selection node (WL);
• and
• a selection transistor (T1) having a gate connected to the selection node (WL) and linking the first electrode (EL1) to the second input/output node (BL), wherein each memory cell has a first (“0”) or a second (“1”) logic state corresponding respectively to different levels of charges stored in the elementary storage component (NVM);
• a read circuit associated with at least one memory cell of the matrix of memory cells, comprising:
• a capacitive transimpedance amplifier stage configured to read a datum stored in a selected memory cell (CMij) of the matrix of memory cells selected via the switching-on of a corresponding selection transistor (T1) by applying a selection signal (VWL) to a selection node (WL), said capacitive transimpedance amplifier stage comprising:
• an operational amplifier (AO) having:
• a first input (e1_ao) connected to the second input/output node (BL) of the selected memory cell, a second input (e2_ao) for receiving a first reference signal (VREF1);
• and an output (s1_ao) for supplying an analog read signal (Vs1_ao);
• and
• a feedback capacitive impedance (CCR) mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier;
• and
• a sequencer circuit configured to, following the reading of a datum corresponding to the second logic state (“1”), apply a control signal (VSL) to the first input/output node (SL) having an amplitude lower than the first reference signal (VREF1) and maintain the selection transistor (T1) in an on state so as to replace, in the elementary storage component (NVM) of the selected memory cell, a level of charges corresponding to the second logic state (“1”).