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US 12,658,228 B2Granted
Memory device including memory package and memory system including the memory device
AssigneeSK hynix Inc.
InventorsSung Geun Kang, In Bo Shim, Su Il Jin, Eun Kyu Choi
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Abstract
A memory system includes a memory device and a memory controller for providing data to the memory device based on a clock signal. The memory device includes a first memory group; a second memory group; an internal clock generator for generating a first internal clock signal and a second internal clock signal, which respectively correspond to a first period and a second period of the clock signal; and a data distributor for providing the data respectively to the first memory group and the second memory group, based on the first internal clock signal and the second internal clock signal.
Claims17
A memory system comprising:
- a memory device;
- and
- a memory controller configured to provide data to the memory device based on a clock signal,
- wherein the memory device includes:
- a first memory group;
- a second memory group;
- an internal clock generator configured to generate a first internal clock signal and a second internal clock signal based on the clock signal, wherein each of the first and second internal clock signals has a period longer than a period of the clock signal, and the first and second internal signals have different phases;
- and
- a data distributor configured to provide the data respectively to the first memory group and the second memory group, based on the first internal clock signal and the second internal clock signal,
- wherein the data includes a first data item and a second data item,
- wherein the data distributor provides the first data item and the second data item respectively to a first memory die included in the first memory group and a second memory die included in the second memory group, based on the first internal clock signal and the second internal clock signal, and
- wherein the first memory die and the second memory die perform, in parallel, program operations of respectively storing the first data item and second data item.
9 more elements
A memory system comprising:
- a memory device;
- and
- a memory controller configured to provide data to the memory device based on a clock signal,
- wherein the memory device includes:
- first to nth memory groups each including a plurality of memory dies;
- an internal clock generator configured to generate first to nth internal clock signals based on the clock signal, wherein each of the first to nth internal clock signals has a period longer than a period of the clock signal, and the first to nth internal signals have different phases;
- and
- a data distributor configured to provide the data to the first to nth memory groups, respectively, based on the first to nth internal clock signals,
- wherein the data distributor provides the data to first memory dies in each of the first to nth memory groups, respectively, based on the first to nth internal clock signals, and
- wherein the first memory dies respectively included in the first to nth memory groups simultaneously perform a program operation of storing the data.
7 more elements
A memory package comprising:
- first to nth memory groups each including a plurality of memory dies;
- an internal clock generator configured to generate first to nth internal clock signals based on a clock signal, and provide the first to nth internal clock signals to the first to nth memory groups, respectively, wherein each of the first to nth internal clock signals has a period longer than a period of the clock signal, and the first to nth internal signals have different phases;
- and
- a data distributor configured to receive data according to the clock signal, and distribute the data to the first to nth memory groups, respectively, based on the first to nth internal clock signals, wherein the data includes first to nth data items,
- wherein the data distributor distributes the first to nth data items to first memory dies in each of the first to nth memory groups, respectively, based on the first to nth internal clock signals, and
- wherein the first memory dies in each of the first to nth memory groups perform, in parallel, program operations of respectively storing the first to nth data items.
3 more elements
Dependencies are inferred from the claim text.