Page buffers and operation methods thereof, memory devices, and memory systems

A memory device, comprising:

• a memory cell array coupled with a plurality of bit lines;
• and
• a plurality of page buffers, a page buffer of the plurality of page buffers coupled with a bit line of the plurality of bit lines and configured to perform a sense operation based on a current level of the bit line,
• wherein the page buffer includes a plurality of latch circuits, a latch circuit of the plurality of latch circuits including:
• a resetting control circuit coupled to a first data node and configured to receive a first supply voltage to determine a potential of the first data node;
• a setting control circuit coupled to a second data node and configured to receive the first supply voltage to determine a potential of the second data node;
• a data transmission circuit coupled to the first data node and the second data node and configured to receive a second supply voltage;
• and
• a latch transmission circuit coupled to the first data node, the second data node, and a sense node, wherein the first supply voltage is higher than the second supply voltage, wherein the latch transmission circuit includes a fifth transistor and a sixth transistor, and wherein:
• a control electrode of the fifth transistor is coupled with the first data node, a first electrode of the fifth transistor is coupled with the second data node, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor;
• and
• a control electrode of the sixth transistor receives a transmission signal, and a second electrode of the sixth transistor is coupled with the sense node.

An operation method of a page buffer, wherein the page buffer comprises:

• a plurality of latch circuits, a latch circuit of the plurality of latch circuits including a resetting control circuit coupled with a first data node, a setting control circuit coupled with a second data node, and a data transmission circuit coupled with both the first data node and the second data node;
• a latch transmission circuit coupled with the first data node, the second data node, and a sense node, wherein the latch transmission circuit includes a fifth transistor and a sixth transistor, and wherein:
• a control electrode of the fifth transistor is coupled with the first data node, a first electrode of the fifth transistor is coupled with the second data node, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor;
• and
• a control electrode of the sixth transistor receives a transmission signal, and a second electrode of the sixth transistor is coupled with the sense node;
• and
• the operation method includes:
• in a reset phase, setting a reset signal to an enabled state, and setting, by the resetting control circuit, the first data node and the second data node to a first logic level and a second logic level, respectively, in response to the enabled state of the reset signal, wherein the first logic level is higher than the second logic level;
• and
• in a read phase, where the sense node is at the first logic level, following the reset phase, setting the transmission signal to the enabled state, and coupling, by the latch transmission circuit, the second data node with the sense node in response to the transmission signal being in the enabled state, so that wherein the sense node changes from the first logic level to the second logic level.