Low power scheme for power down in integrated dual rail SRAMs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSanjeev Kumar Jain
Life of this patent
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Abstract
Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.
Claims20
A circuit comprising:
- a power detector configured to generate an isolated power signal when a voltage on a first voltage rail is below a threshold voltage;
- and
- logic circuitry configured to receive the isolated power signal and to output an enabling signal for disabling a clock generator, wherein the logic circuitry comprise a level shifter for a clock signal and a level shifter for the enabling signal.
A method comprising:
- powering down a first voltage rail while a second voltage rail remains powered on, wherein the first and second voltage rails are configured to power different portions of a memory device, each of the first and second voltage rails has a voltage level higher than a ground voltage, and powering down the first voltage rail comprises:
- receiving an isolated signal to disable a clock generator.
A circuit comprising:
- means for detecting a voltage on a first power rail;
- and
- logic circuitry configured to disable a clock generator when the voltage detected by the means for detecting a voltage on a first power rail is below a threshold voltage, wherein the logic circuitry comprise a first level shifter for a clock signal and a second level shifter for an enable signal.
Dependencies are inferred from the claim text.