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US 12,657,447 B1Granted
Neural cluster and neural processing SoC including the same
AssigneeRebellions Inc.
InventorsWongyu Shin, Juyeong Yoon, Jinseok Kim
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Abstract
According to one or more embodiments of the present disclosure, a neural cluster includes a plurality of neural core units each including a neural core configured to process a neural network operation, a plurality of shared memory units each including a shared memory shared by the plurality of neural core units, and a mesh network for connecting the plurality of neural core units and the plurality of shared memory units, wherein the plurality of shared memory units are arranged in a central portion of the neural cluster, and the plurality of neural core units are arranged symmetrically above and below a shared memory area where the plurality of shared memory units are arranged.
Claims17
A neural cluster, comprising:
- a plurality of neural core units each including a neural core configured to process a neural network operation;
- a plurality of shared memory units each including a shared memory shared by the plurality of neural core units;
- and
- a mesh network for connecting the plurality of neural core units and the plurality of shared memory units,
- wherein the plurality of shared memory units are arranged in a central portion of the neural cluster, and the plurality of neural core units are arranged symmetrically above and below a shared memory area where the plurality of shared memory units are arranged,
- wherein the mesh network includes a plurality of routers each arranged at an intersection formed by a row line and a column line, and a mesh network bus, and
- wherein each of the plurality of routers is connected to one of the plurality of neural core units or one of the plurality of shared memory units through the mesh network bus, and wherein each of the plurality of routers includes:
- a first port configured to receive a first data packet having a first flag;
- a second port configured to receive a second data packet having a second flag and having the same destination as the first data packet;
- a third port connected to the destination of the first data packet and the second data packet;
- and
- an arbiter configured to determine whether an atomic transfer is applied to each of the first data packet and the second data packet, based on the first flag and the second flag.
9 more elements
A neural cluster, comprising:
- a first neural core unit including a first neural core configured to process a neural network operation;
- a second neural core unit including a second neural core configured to process a neural network operation;
- a first shared memory unit including a first shared memory shared by the first neural core unit and the second neural core unit;
- a second shared memory unit including a second shared memory shared by the first neural core unit and the second neural core unit;
- and
- a mesh network for connecting the first neural core unit, the second neural core unit, the first shared memory unit, and the second shared memory unit,
- wherein the first neural core is configured to generate a first data access request in a first cycle and generate a second data access request in a second cycle,
- wherein the second neural core is configured to generate a third data access request in the first cycle and generate a fourth data access request in the second cycle,
- wherein the first to fourth data access requests are respectively interleaved and transmitted as distributed to the first shared memory and the second shared memory, and
- wherein the first shared memory unit and the second shared memory unit are arranged in a central portion of the neural cluster, and the first neural core unit and the second neural core unit are respectively arranged symmetrically above and below a shared memory area where the first shared memory unit and the second shared memory unit are arranged.
7 more elements
A neural processing SoC (System on a Chip), comprising:
- a first neural cluster;
- and
- a second neural cluster,
- wherein each of the first neural cluster and the second neural cluster includes:
- a plurality of neural core units each including a neural core configured to process a neural network operation;
- a plurality of shared memory units each including a shared memory shared by the plurality of neural core units;
- and
- a mesh network for connecting the plurality of neural core units and the plurality of shared memory units,
- wherein the plurality of shared memory units are arranged in a central portion of each of the first neural cluster and the second neural cluster, and the plurality of neural core units are arranged symmetrically above and below a shared memory area where the plurality of shared memory units are arranged, and
- wherein a plurality of shared memories of the first neural cluster are shared by the plurality of neural core units of the second neural cluster,
- wherein the mesh network includes a plurality of routers each arranged at an intersection formed by a row line and a column line, and a mesh network bus, and
- wherein each of the plurality of routers is connected to one of the plurality of neural core units or one of the plurality of shared memory units through the mesh network bus, and wherein each of the plurality of routers includes:
- a first port configured to receive a first data packet having a first flag;
- a second port configured to receive a second data packet having a second flag and having the same destination as the first data packet;
- a third port connected to the destination of the first data packet and the second data packet;
- and
- an arbiter configured to determine whether an atomic transfer is applied to each of the first data packet and the second data packet, based on the first flag and the second flag.
14 more elements
A neural processing SoC, comprising:
- a first neural cluster;
- and
- a second neural cluster,
- wherein each of the first neural cluster and the second neural cluster includes:
- a first neural core unit including a first neural core configured to process a neural network operation;
- a second neural core unit including a second neural core configured to process a neural network operation;
- a first shared memory unit including a first shared memory shared by the first neural core unit and the second neural core unit;
- a second shared memory unit including a second shared memory shared by the first neural core unit and the second neural core unit;
- and
- a mesh network for connecting the first neural core unit, the second neural core unit, the first shared memory unit, and the second shared memory unit,
- wherein the first neural core is configured to generate a first data access request in a first cycle and generate a second data access request in a second cycle,
- wherein the second neural core is configured to generate a third data access request in the first cycle and generate a fourth data access request in the second cycle,
- wherein the first to fourth data access requests are respectively interleaved and transmitted as distributed to the first shared memory and the second shared memory,
- wherein the first shared memory unit and the second shared memory unit are arranged in a central portion of each of the first neural cluster and the second neural cluster, and the first neural core unit and the second neural core unit are respectively arranged symmetrically above and below a shared memory area where the first shared memory unit and the second shared memory unit are arranged, and
- wherein the first shared memory and the second shared memory of the first neural cluster are shared by the first neural core unit and the second neural core unit of the second neural cluster.
12 more elements
Dependencies are inferred from the claim text.