Fault diagnostics
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSandeep Kumar Goel, Ankita Patidar
Life of this patent
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Abstract
Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.
Claims20
A method comprising:
- receiving a layout of a circuit comprising a plurality of cells, the layout comprising placement information of a first cell and a second cell of the circuit;
- determining a cell orientation for each of the first cell and the second cell;
- determining a base orientation for each of the first cell and the second cell from the cell orientation;
- determining, from the base orientation, a bridge pair comprising a first boundary node of the first cell facing a second boundary node of the second cell;
- modeling of the bridge pair as another circuit;
- and
- generating a test pattern for the modeled bridge pair.
An apparatus comprising:
- a memory storage;
- and
- a processing unit coupled to the memory storage, wherein the processing unit is operative to:
- receive a circuit layout comprising placement information of the plurality of cells of the circuit;
- identify, from the placement information, a first cell abutting a second cell from the circuit layout, the second cell being separated from the first cell by a boundary circuit;
- identify a bridge pair between the first cell and the second cell, the bridge pair comprising a first boundary node of the first cell paired with a second boundary node of the second cell;
- model the bridge pair as another circuit comprising a resistive element connected to a predetermined potential;
- and
- generate a test pattern for the modeled bridge pair.
A non-transitory computer-readable medium that stores a set of instructions which when executed perform a method comprising:
- receiving a layout of a circuit comprising a plurality of cells, the layout comprising placement information of the plurality of cells of the circuit;
- identifying a bridge pair in the circuit from the layout, wherein identifying the bridge pair comprises:
- identifying a first cell abutting a second cell from the layout, the second cell being separated from the first cell by a boundary circuit, and
- identifying the bridge pair between the first cell and the second cell, the bridge pair comprising a first boundary node of the first cell paired with a second boundary node of the second cell;
- determining whether to model the bridge pair as another circuit;
- and
- generating a test pattern for the bridge pair.
Dependencies are inferred from the claim text.