System and method for generation of networks-on-chip (NoCs)
AssigneeArteris, Inc.
InventorsAmir Charif, Xavier Van Ruymbeke
Life of this patent
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Abstract
System and methods are disclosed that are implemented by a tool for generation and synthesis of networks, such as a network-on-chip (NoC). The tool receives input from the user, either as a data file or through input in a graphical user interface (display). The tool generates a NoC from a set of physical constraints and performance constraints. The tool produces the NoC with all its elements, which is a legal and meets the constraints. The tool also receives as an input performance scenarios or performance requirement that can be used to transform an existing topology to satisfy the newly added requirements. The resulting output represents the network, such as the NoC, that meets the requirements.
Claims6
A tool for generation of a network-on-chip (NoC) topology using performance constraints, wherein the tool includes a non-transitory computer readable medium for storing code, which when executed by one or more processors, would cause the tool to:
- receive a traffic classification identified for a plurality of connections between initiators and targets;
- receive a set of traffic patterns selected from a plurality of pre-defined traffic patterns;
- analyze a set of connections between the initiators and the targets to generate a plurality of scenarios based on the set of connections included in the traffic classification;
- and
- use the plurality of scenarios to alter the NoC with each of the plurality of scenarios in order to incrementally modify the NoC while sustaining the performance constraints.
Dependencies are inferred from the claim text.