Memory bandwidth control in a core
AssigneeIntel Corporation
InventorsVedvyas Shanbhogue, Krishnakumar Ganapathy, Venkateswara Madduri, James Allen, James Coleman, Stephen Robinson
Life of this patent
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Abstract
Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.
Claims20
An apparatus comprising:
- a plurality of per thread quality of service (QoS) model specific registers (MSRs), wherein each QoS MSR is associated with a single thread;
- a platform level MSR to index into the thread QOS MSRs;
- a memory bandwidth monitor per thread local to a core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a value for a first class of service stored in a field of its associated thread QoS MSR of the plurality of thread QoS MSRs, the class of service pointed to by the platform level MSR, wherein each of the thread QoS MSRs is to store a value for a plurality of classes of service including the value for the first class of service;
- and
- execution resources to support execution of at least one thread of the core.
A system comprising:
- a core including:
- a plurality of per thread quality of service (QOS) model specific registers (MSRs),
- wherein each QoS MSR is associated with a single thread;
- a platform level MSR to index into the thread QOS MSRs;
- a memory bandwidth monitor per thread local to a core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a value for a first class of service stored in a field of its associated thread QoS MSR of the plurality of thread QoS MSRs, the class of service pointed to by the platform level MSR, wherein each of the thread QoS MSRs is to store a value for a plurality of classes of service including the value for the first class of service, and
- execution resources to support execution of at least one thread of the core;
- and
- memory coupled to the core.
Dependencies are inferred from the claim text.