Dynamically changing data access bandwidth by selectively enabling and disabling data links

A memory controller to control a dynamic random access memory (DRAM) device, the memory controller comprising:

• a set of driver circuits to transmit data to the DRAM device, including a first subset of driver circuits and a second subset of driver circuits, wherein the first subset and the second subset are disjoint sets;
• and
• a control interface to transmit mode information indicating one of a first mode or a second mode, wherein:
• in the first mode, each of the first subset of driver circuits and the second subset of driver circuits is enabled to communicate data with the DRAM device;
• and
• in the second mode, the first subset of driver circuits is enabled to communicate data with the DRAM device, while the second subset of driver circuits is disabled such that the second subset of driver circuits does not communicate with the DRAM device, wherein a common signaling rate is used for data communication in both the first mode and the second mode.

A method of operating a memory controller to communicate data with a memory device via a plurality of data links, the memory controller including a data interface having a first set of driver circuits coupled to a first subset of the plurality of data links and a second set of driver circuits coupled to a second subset of the plurality of data links, the first subset and the second subset being disjoint sets, the method comprising:

• operating in a first bandwidth mode by enabling each of the first set of driver circuits and the second set of driver circuits to communicate data with the memory device;
• transitioning to a second bandwidth mode by disabling the second set of driver circuits while maintaining the first set of driver circuits enabled to communicate data with the memory device;
• transmitting, from the memory controller to the memory device via a control interface, mode information indicating a transition from the first bandwidth mode to the second bandwidth mode;
• and
• maintaining a common signaling rate for data communication with the memory device via the first set of driver circuits during both the first bandwidth mode and second bandwidth mode.