Circuit screening system and circuit screening method

A circuit screening system, comprising:

• a target circuit under test, including a plurality of flip-flops in cascade connection and a cluster of logic circuits coupled to the flip-flops;
• a power circuit, configured to provide a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage is located in an input range in a first period, deviates from the input range in a second period after the first period, and located in the input range in a third period after the second period;
• and
• a clock generating circuit, arranged to provide a clock signal to the target circuit under test;
• wherein the clock signal has a first profile and a second profile in the first period and the third period, respectively, and the first profile and the second profile has a phase difference.

A circuit screening method, comprising:

• operating in a first input stage, in which a first testing signal is inputted into a target circuit under test, and a clock signal having a first profile is provided to the target circuit under test;
• operating in a second input stage after the first input stage, in which a second testing signal different from the first testing signal is inputted into the test target circuit under test, and a clock signal having a second profile different from the first profile is provided to the target circuit under test;
• wherein the first profile and the second profile has a phase difference;
• wherein in the first input stage and the second input stage, a supply voltage, whose voltage level locates in an input range, is provided to the target circuit under test, and the circuit screening method further comprises:
• operating in a first stress stage after the first input stage, in which the voltage level of the supply voltage locates in a stress range higher than the input range.