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US 12,653,035 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsInhyung Song, Jongyoun Kim, Shanghoon Seo
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes: an encapsulation layer sealing at least one semiconductor chip; a redistribution level layer arranged on the encapsulation layer; a laser mark metal layer arranged on the redistribution level layer; and a laser mark arranged inside the laser mark metal layer. The laser mark includes letters, numbers, figures, symbols, and recognition codes indicating various pieces of information of the semiconductor package.
Claims20
A semiconductor package comprising:
- an encapsulation layer sealing at least one semiconductor chip;
- a redistribution level layer arranged on the encapsulation layer;
- a laser mark metal layer arranged on the redistribution level layer;
- and
- a laser mark arranged inside the laser mark metal layer,
- wherein the laser mark metal layer comprises a plurality of sub-metal layers stacked on top of each other.
3 more elements
A semiconductor package comprising:
- a fan-in region in which a semiconductor chip is located, and a fan-out region surrounding the fan-in region and comprising a package element including an inner wiring layer;
- a package body level layer comprising a fan-in encapsulation layer sealing the semiconductor chip in the fan-in region;
- a first redistribution level layer arranged on a lower surface of the package body level layer and comprising a first redistribution layer and a first redistribution insulating layer, wherein the first redistribution layer extends from the fan-in region to the fan-out region, and the first redistribution insulating layer insulates the first redistribution layer;
- a second redistribution level layer arranged on an upper surface of the package body level layer and comprising a second redistribution layer and a second redistribution insulating layer, wherein the second redistribution layer extends from the fan-in region to the fan-out region, and the second redistribution insulating layer insulates the second redistribution layer;
- a laser mark metal layer arranged on the second redistribution level layer;
- and
- a laser mark arranged inside the laser mark metal layer,
- wherein the laser mark metal layer comprises a plurality of sub-metal layers stacked on top of each other, and the plurality of sub-metal layers comprises a first sub-metal layer and a second sub-metal layer made of different materials.
5 more elements
A semiconductor package comprising:
- a fan-in region in which a semiconductor chip is located, and a fan-out region surrounding the fan-in region and including an inner wiring layer;
- a package body level layer comprising an encapsulation layer sealing the semiconductor chip in the fan-in region and the inner wiring layer in the fan-out region;
- a first redistribution level layer arranged on a lower surface of the package body level layer and comprising a first redistribution layer and a first redistribution insulating layer, wherein first redistribution layer extends from the fan-in region to the fan-out region, and the first redistribution insulating layer insulates the first redistribution layer;
- a second redistribution level layer arranged on an upper surface of the package body level layer and comprising a second redistribution layer and a second redistribution insulating layer, wherein the second redistribution layer extends from the fan-in region to the fan-out region, and the second redistribution insulating layer insulates the second redistribution layer;
- a laser mark metal layer arranged on the second redistribution level layer in the fan-in region and configured to have a plurality of sub-metal layers;
- and
- a laser mark arranged on the laser mark metal layer,
- wherein in a top plan view, the laser mark metal layer is disposed inside of the semiconductor chip and the laser mark is disposed inside of the laser mark metal layer.
5 more elements
Dependencies are inferred from the claim text.