Advanced interconnection for wafer on wafer packaging

A semiconductor device assembly, comprising:

• a first module having one or more memory arrays, each of the one or more memory arrays being connected to a plurality of landing pads of the first module;
• and
• a second module having complementary metal-oxide-semiconductor (CMOS) devices, the second module comprising:
• a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second module,
• a plurality of metal routing layers connected to corresponding CMOS devices, and
• a plurality of via contacts each being connected to a corresponding one of the plurality of metal routing layers of the second module and a corresponding one of the plurality of landing pads of the first module;
• wherein each of the plurality of the via contacts passes through a corresponding one of the plurality of socket STI regions,
• wherein a frontside surface of the first module and a frontside surface of the second module are bonded to form a wafer-on-wafer (WOW) bonding.

A method of forming a semiconductor device assembly, comprising:

• providing a first wafer having one or more memory arrays and a plurality of landing pads, the one or more memory arrays being connected to the plurality of landing pads respectively;
• providing a second wafer including complementary metal-oxide-semiconductor (CMOS) devices, a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second wafer, and a plurality of metal routing layers connected to corresponding CMOS devices;
• bonding a frontside surface of the first wafer to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding;
• thinning the second wafer from its backside surface;
• etching a plurality of a first type of via holes and a plurality of a second type of via holes from the backside surface of the second wafer, each of the plurality of the first type of via holes being etched to a corresponding one of the plurality of metal routing layers, and each of the plurality of the second type of via holes being etched to a corresponding one of the plurality of landing pads;
• filling a conductive material into the plurality of the first type of via holes and the plurality of the second type of via holes to form a plurality of a first type of via contacts and a plurality of a second type of via contacts, respectively;
• and
• forming a plurality of routing layers each being connected to one of the plurality of the first type of via contacts and a corresponding one of the plurality of the second type of via contacts.