High band-gap devices with a doped high band-gap gate electrode extension
AssigneeTexas Instruments Incorporated
InventorsDong Seup Lee, Chang Soo Suh
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Abstract
A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of p-type GaN semiconductor material. The GaN FET includes a gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode. The gate electrode extension of p-type GaN semiconductor material in electrical contact with the gate electrode may improve the GaN FET characteristics such as off state leakage, subthreshold voltage and post stress Vt shift.
Claims20
A microelectronic device, comprising:
- a gallium nitride field effect transistor (GaN FET), including:
- a channel layer of III-N material;
- a barrier layer of III-N material over the channel layer;
- a p-type GaN layer on the barrier layer;
- a gate metal layer on the p-type GaN layer;
- a gate including a first portion of the p-type GaN layer and a first portion of the gate metal layer on the first portion of the p-type GaN layer;
- and
- a p-type GaN gate electrode extension including a second portion of the p-type GaN layer and a second portion of the gate metal layer on the second portion of the p-type GaN layer, wherein,
- the second portion of the p-type GaN layer is contiguous to the first portion of the p-type GaN layer, and the second portion of the gate metal layer is contiguous to the first portion of the gate metal laver;
- and
- the p-type GaN gate electrode extension extends beyond the gate, but is inside of an isolation region laterally surrounding the GaN FET.
A method of forming a microelectronic device with a gallium nitride field effect transistor (GaN FET), comprising:
- forming a channel layer of III-N semiconductor material;
- forming a barrier layer of III-N semiconductor material over the channel layer;
- forming a p-type GaN layer over the barrier layer;
- forming a gate metal layer on the p-type GaN layer;
- forming an isolation region encircling the GaN FET;
- and
- patterning the gate metal layer and the p-type GaN layer to form a gate of the GaN FET and a p-type GaN gate electrode extension contiguous to the gate, wherein:
- the gate includes a first portion of the p-type GaN layer and a first portion of the gate metal layer;
- and
- the p-type GaN gate electrode extension extends beyond the gate, but is inside of the isolation region, the p-type GaN gate electrode extension including a second portion of the p-type GaN layer contiguous to the first portion of the p-type GaN layer and a second portion of the gate metal layer contiguous to the first portion of the gate metal layer.
Dependencies are inferred from the claim text.