Semiconductor device and power conversion device

A semiconductor device comprising:

• a semiconductor substrate having a drift layer of a first conductivity type;
• a plurality of trenches formed on an upper surface of the semiconductor substrate and extending in a first direction along the upper surface of the semiconductor substrate;
• a body region of a second conductivity type different from the first conductivity type, the body region being formed on a side surface of the trench in a lateral direction;
• a source region of the first conductivity type, the source region being formed on the upper surface of the semiconductor substrate and formed in the body region;
• a JFET region of the first conductivity type, the JFET region being formed on an upper surface of the drift layer and having side surfaces on both sides in contact with the body region;
• a drain region of the first conductivity type, the drain region being formed on a lower surface of the semiconductor substrate and electrically connected to the drift layer;
• and
• a gate electrode formed in the trench and on the upper surface of the semiconductor substrate via an insulating film,
• wherein, in a unit cell, some of the plurality of trenches are arranged in a second direction intersecting with the first direction in a plan view to form a first trench group, and another some of the plurality of trenches are arranged in the second direction to form a second trench group,
• the trenches forming the first trench group and the trenches forming the second trench group are arranged side by side in the first direction,
• the source region is also formed between the trenches adjacent to each other in the second direction,
• a channel region formed at a depth shallower than a depth of the trench is provided on a lower surface of the source region formed between the trenches adjacent to each other in the second direction,
• the gate electrode includes
• a first portion buried in each of the plurality of trenches, and
• a second portion located on the upper surface of the semiconductor substrate, connecting first portions arranged in the first direction to each other, and connecting the first portions arranged in the second direction to each other, and
• plurality of JFET regions is provided per unit cell.