Nanosheet transistors with buried power rails

A semiconductor array structure comprising:

• a substrate;
• a plurality of field effect transistors formed on the substrate, each comprising a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region adjacent the gate and between the first and second source-drain regions, the plurality of field effect transistors being arranged in lateral rows;
• a plurality of buried power rails, buried in the substrate, each having a top at a level lower than the channel regions, each having buried power rail sidewalls;
• a plurality of shared contacts electrically interconnected with the buried power rails and the second source-drain regions;
• bottom dielectric isolation located between and electrically isolating the substrate and the first and second source-drain regions of the plurality of field effect transistors;
• electrically isolating regions directly adjacent and separating the bottom dielectric isolation and the buried power rail sidewalls of each of the plurality of buried power rails, and separating the buried power rails from the substrate, the electrically isolating regions including a shallow trench isolation liner in direct contact with the substrate and the bottom dielectric isolation;
• and
• an inter-layer dielectric located directly adjacent to the first and second source-drain regions of the plurality of field effect transistors, the plurality of shared contacts, and a contact etch-stop liner sandwiched between the inter-layer dielectric the electrically isolating regions,
• wherein the buried power rails are located between adjacent rows of the field effect transistors;
• and
• wherein first adjacent pairs of the lateral rows are n-type and second adjacent pairs of the lateral rows are p-type.