Method of forming semiconductor memory device
AssigneesUnited Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.
InventorsYi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
Life of this patent
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Abstract
A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
Claims9
A method of forming a semiconductor memory device, comprising:
- providing a substrate;
- forming a plurality of gates in the substrate, extending along a first direction;
- forming an insulating layer, on the substrate, covering the gates;
- forming a plurality of bit lines on the insulating layer, extending in a second direction being perpendicular to the first direction;
- and
- forming a plug under each of the bit lines, between two adjacent ones of the gates, the plug physically contacting each of the bit lines;
- wherein forming the plug and the bit lines further comprising:
- forming a semiconductor layer on the insulating layer;
- forming a protection layer on the semiconductor layer;
- forming a plug hole in the protection layer and the semiconductor layer;
- forming a conductive layer on the semiconductor layer to fill in the plug hole and to have a lower sunken top surface above the plug hole;
- performing a mechanical polishing process to remove the conductive layer having the lower sunken top surface, the protection layer and peripheral taper protrusion portions of the plug, to form the plug having a planar top surface flush with a top surface of the semiconductor layer, wherein a portion of the semiconductor layer around the plug is in direct contact with a sidewall of the plug;
- and
- forming a stacked structure on the planar top surface of the plug and on the top surface of the semiconductor layer, to form the bit lines.
Dependencies are inferred from the claim text.