Memory device having a barrier layer between a bit line contact and a top electrode
AssigneeNanya Technology Corporation
InventorJhen-Yu Tsai
Life of this patent
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Abstract
A manufacturing method of a memory device includes forming a capacitor in a first dielectric layer, and forming a bottom electrode over the capacitor. A word line and a second dielectric layer are formed over the bottom electrode and the first dielectric layer, in which the word line is embedded in the second dielectric layer. A bit line contact is formed over the second dielectric layer, in which a vertical projection of the bit line contact on the first dielectric layer is spaced apart a vertical projection of the bottom electrode on the first dielectric layer. After forming the bit line contact, a channel in contact with the bottom electrode and the word line is formed. A top electrode is formed over the channel and in contact with the bit line contact.
Claims10
A memory device, comprising:
- a first dielectric layer;
- a capacitor in the first dielectric layer;
- a bottom electrode over the capacitor;
- a channel over the bottom electrode;
- a top electrode over the channel;
- a gate dielectric layer surrounding the channel;
- a word line surrounding the gate dielectric layer;
- a second dielectric layer surrounding the word line, the gate dielectric layer and the channel;
- a bit line contact over the second dielectric layer, wherein a vertical projection of the bit line contact on the first dielectric layer is spaced apart a vertical projection of the channel on the first dielectric layer;
- and
- a barrier layer between the bit line contact and the top electrode.
Dependencies are inferred from the claim text.