Interlocking structure for crosstalk reduction and method of manufacture
AssigneeAstera Labs, Inc.
InventorsAbhinaya Easwari Mohan, Zengji Zhao, Yiqi Tang
Life of this patent
Estimating the term…
Abstract
An electronic system having a mounting substrate with a plurality of layers. The mounting substrate combines an upper shield structure and a lower shield structure to form an interlocking shielding structure to reduces crosstalk interference and improve return loss and insertion loss for high-speed serial communication circuits. The upper shield structure and the lower shield structure have a series of grounded reference shields that reduce unwanted electrical signal interferences.
Claims20
A method of manufacture of an electronic system comprising:
- forming a lower shield structure over a base layer in a mounting substrate, the lower shield structure having a lower reference shield over a lower void volume;
- forming an upper shield structure over the lower shield structure, the upper shield structure having an upper reference shield over an upper void volume, the upper reference shield and the lower reference shield interlocking to form an interlocking shielding structure horizontally covering the upper void volume and the lower void volume;
- forming a top conductor structure on a top layer of the mounting substrate, the top conductor structure having a surface pad electrically coupled to a via;
- and
- forming a bottom conductor structure having a solder ball on a bottom layer, the interlocking shielding structure positioned directly between the top conductor structure and the bottom conductor structure.
A method of manufacture of an electronic system comprising:
- forming a lower layer on a base layer in a mounting substrate, the lower layer having a dielectric portion and a conductive portion, the lower layer includes a lower shield structure having a lower reference shield over a lower void volume, the lower reference shield electrically coupled to a ground line;
- forming an upper layer over the lower layer, the upper layer having a dielectric portion and a conductive portion, the upper layer includes an upper shield structure having an upper reference shield over an upper void volume, the upper reference shield and the lower reference shield interlocking to form an interlocking shielding structure horizontally covering the upper void volume and the lower void volume, and the upper shield structure electrically coupled to a ground line;
- forming a top conductor structure on a top layer of the mounting substrate, the top conductor structure having a surface pad electrically coupled to a via;
- forming a bottom conductor structure having a solder ball on a bottom layer, the interlocking shielding structure positioned directly between the top conductor structure and the bottom conductor structure;
- and
- attaching a ball grid array component to the solder ball.
An electronic system comprising:
- a mounting substrate further comprising:
- a base layer;
- a lower shield structure over the base layer, the lower shield structure having a lower reference shield over a lower void volume;
- an upper shield structure over the lower shield structure, the upper shield structure having an upper reference shield over an upper void volume, and the upper reference shield and the lower reference shield interlocking to form an interlocking shielding structure horizontally covering the upper void volume and the lower void volume;
- a top conductor structure on a top layer of the mounting substrate, the top conductor structure having a surface pad electrically coupled to a via;
- and
- a bottom conductor structure having a solder ball on a bottom layer of the mounting substrate, the interlocking shielding structure positioned directly between the top conductor structure and the bottom conductor structure.
Dependencies are inferred from the claim text.