Linear prediction to suppress spurs in a digital phase-locked loop

A phase-locked loop comprising:

• an input configured to receive an input clock signal and an output configured to output a phase-adjusted clock signal;
• an error detector configured to output an error signal based on the input clock signal and a frequency-divided feedback clock signal, the phase-locked loop being configured to generate the phase-adjusted clock signal based on the error signal;
• and
• a linear predictive coding filter coupled between the input and the output of the phase-locked loop and configured to reduce spurious energy in the phase-adjusted clock signal, the linear predictive coding filter configured to determine a plurality of weights of an all-pole transfer function based on digital values input to the linear predictive coding filter, a plurality of poles in the all-pole transfer function corresponding to locations of spurious energy.

A method for generating a phase-adjusted clock signal utilizing a phase-locked loop, the method comprising:

• receiving an input clock signal;
• detecting an error signal based on the input clock signal and a frequency-divided feedback clock signal;
• generating the phase-adjusted clock signal based on the error signal;
• and
• applying a digital filter to reduce spurious energy in the phase-adjusted clock signal, the digital filter having a plurality of weights each corresponding to a respective spur.