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US 12,652,053 B2Granted
Clock buffer
AssigneeRambus Inc.
InventorsPanduka Wijetunga, Catherine Chen
Life of this patent
Estimating the term…
Abstract
A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.
Claims20
An integrated circuit, comprising:
- an input clock interface to receive an input clock signal;
- a first output clock signal interface to transmit a first output clock signal with a first feedback loop adjusted timing offset between the input clock signal and the first output clock signal;
- alignment feedback loop circuitry to produce a synthesized clock signal based on the input clock signal, the alignment feedback loop circuitry to also, based on the synthesized clock signal, produce a first delayed clock signal;
- first latch receiver circuitry to indicate a first delay error between the input clock signal and the first output clock signal;
- and
- first delay circuitry having a first variable delay to adjust a first timing of the first output clock signal relative to the synthesized clock signal based on the first delay error.
3 more elements
An integrated circuit, comprising:
- clock synthesis feedback loop circuitry to produce a synthesized clock signal locked to an input clock signal;
- first delay circuitry, having a first delay, to produce, based on the synthesized clock signal, a delayed synthesized clock signal;
- second delay circuitry, having a first variable delay, to produce, based on the delayed synthesized clock signal, a first output clock signal;
- synthesized clock signal alignment feedback loop circuitry to, based on the synthesized clock signal, produce an aligned synthesized clock signal;
- first latch receiver circuitry to provide, based on the aligned synthesized clock signal and the first output clock signal, produce a plurality of delay indicators indicating timing differences between the first output clock signal and the aligned synthesized clock signal;
- and
- delay adjustment circuitry to, based on the plurality of delay indicators, adjust the first variable delay.
4 more elements
A method, comprising:
- receiving, via an input clock interface, an input clock signal;
- transmitting, via a first output clock signal interface, a first output clock signal;
- adjusting, with a first feedback loop, a first timing offset between the input clock signal and the first output clock signal;
- producing a synthesized clock signal based on the input clock signal;
- producing a first delayed clock signal based on the synthesized clock signal;
- comparing the input clock signal and the first output clock signal using first latch receiver circuitry to indicate a first delay error between the input clock signal and the first output clock signal;
- and
- adjusting, based on the first delay error, a first variable delay that affects a first timing of the first output clock signal relative to the synthesized clock signal.
5 more elements
Dependencies are inferred from the claim text.