Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
OwnerJin-Yuan Lee, Mou-Shiung Lininventors
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Abstract
A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.
Claims29
A chip package comprising:
- a ball-grid-array (BGA) substrate;
- a plurality of solder balls on a bottom surface of the ball-grid-array (BGA) substrate and at a bottom of the chip package;
- and
- a first sub-level package over and bonded to the ball-grid-array (BGA) substrate, wherein the first sub-level package comprises:
- a first interconnection scheme comprising:
- a first polymer layer,
- a first interconnection metal layer having a first portion in a first opening in the first polymer layer, wherein the first interconnection metal layer comprises a first copper layer having a first portion in the first opening,
- a second interconnection metal layer over the first polymer layer and first interconnection metal layer, wherein the second interconnection metal layer comprises a second copper layer and a first adhesion metal layer at a bottom of the second copper layer, wherein the first adhesion metal layer has a different material from copper,
- a second polymer layer between the first and second interconnection metal layers,
- a third polymer layer on the second interconnection metal layer and at a top of the first interconnection scheme, wherein a second opening in the third polymer layer is vertically over a top surface of a first metal pad of the second interconnection metal layer, and
- a second metal pad in the second opening and on a top surface of the third polymer layer, wherein the second metal pad comprises a first portion of a third copper layer and a first portion of a second adhesion metal layer at a bottom of the first portion of the third copper layer, wherein the first portion of the third copper layer is in the second opening and over the top surface of the third polymer layer, wherein the first portion of the second adhesion metal layer is on the top surface of the first metal pad and the top surface of the third polymer layer, between the first portion of the third copper layer and the top surface of the first metal pad and between the first portion of the third copper layer and the top surface of the third polymer layer,
- a first metal bump under and in contact with the first portion of the first interconnection metal layer in the first opening in the first polymer layer, wherein the first metal bump is bonded to the ball-grid-array (BGA) substrate and comprises a first tin-containing solder bump, and
- a first integrated-circuit (IC) chip over the top of the first interconnection scheme, wherein the first integrated-circuit (IC) chip comprises a first silicon substrate and a second metal bump under the first silicon substrate, at a bottom of the first integrated-circuit (IC) chip and bonded to the second metal pad, wherein the second metal bump comprises a second tin-containing solder bump.
Dependencies are inferred from the claim text.