US 12,652,045 B2 · Semiconductor device, semiconductor system, and method of controlling semiconductor device

Abstract

A semiconductor device includes a first circuit, a first pad, a first comparator, a second comparator, and a control circuit. The first circuit is configured to pull up a voltage of a first node, and includes a plurality of first transistors connected in parallel to the first node. The first pad is connected to the first node. The first comparator is configured to compare a voltage of the first node with a first reference voltage. The second comparator is configured to compare the voltage of the first node with a second reference voltage. The control circuit is configured to control the plurality of first transistors based on an output of the first comparator and an output of the second comparator.

Claims19

Dependent claims

A semiconductor device comprising:

a first circuit configured to pull up a voltage of a first node, the first circuit including a plurality of first transistors connected in parallel to the first node;
a first pad connected to the first node;
a first comparator configured to compare a voltage of the first node with a first reference voltage;
a second comparator configured to compare the voltage of the first node with a second reference voltage;
a control circuit configured to control the plurality of first transistors based on an output of the first comparator and an output of the second comparator;
and
a voltage divider circuit configured to output one of the first and second reference voltages selected based on control of the control circuit.

4 more elements

A method of controlling a semiconductor device including:

a first circuit connected to a first node and configured to pull up a voltage of the first node;
and
a first pad connected to the first node and to a resistance element provided outside the semiconductor device, the method comprising:
performing a first calibration of output impedance of the semiconductor device for a first period of time;
and
performing a second calibration of the output impedance of the semiconductor device for a second period of time longer than the first period of time,
wherein the first calibration comprises:
comparing a voltage of the first node with each of a first reference voltage and a second reference voltage;
and
controlling the first circuit to vary the voltage of the first node, based on a relation between the voltage of the first node and the first reference voltage and a relation between the voltage of the first node and the second reference voltage.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/594,589Filed 4 Mar 2024

Priority

JP 2023-04208316 Mar 2023

Published

US 2024/0313776 A119 Sep 2024

Granted

9 Jun 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 19/0005
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: modifications of input or output impedance
H03K 19/00384
Modifications for compensating variations of temperature, supply voltage or other physical parameters: in field effect transistor circuits
H03K 19/018557
Using field effect transistors only: coupling arrangements; Impedance matching circuits
H03K
Pulse technique

Semiconductor device, semiconductor system, and method of controlling semiconductor device

Life of this patent

Semiconductor device, semiconductor system, and method of controlling semiconductor device

Life of this patent

Abstract

Claims19