Cascading of bucket brigade delay devices

An apparatus for providing a discrete-time delay of an analog signal, comprising:

• a sample and hold circuit configured for receiving an incoming analog signal which is sampled through a first switch to charge a charge-holding capacitance, after which the switch is opened, and a voltage is retained on the charge-holding capacitance;
• a gain control circuit which through a second switch connects an additional gain capacitance in parallel with the charge-holding capacitance, whereby a forward voltage gain is achieved;
• a delay chain comprising bucket-brigade stages in which charge is passed through switches from one capacitive stage to another, thereby delaying the incoming analog signal before it is output from the delay chain;
• wherein said sample and hold circuit, gain control circuit, and delay chain are part of a first bucket-brigade device (BBD) which is configured for connecting through an attenuation coupling network which matches the output offset of the forward voltage gain achieved by the gain control circuit of said first BBD to the input bias requirement of a subsequent BBD;
• wherein the gain control circuit in a BBD acts in cooperation with the attenuation coupling network to allow cascading sequential BBD devices without the need of a reconstruction filter, or DC blocking, or biasing circuits between each sequential BBD, which in combination provide an extended analog discrete-time delay.

A system for providing a discrete-time delay of an analog signal, comprising:

• a sample and hold circuit configured for receiving an incoming analog signal which is sampled through a first switch to charge a charge-holding capacitance, after which the switch is opened, and a voltage is retained on the charge-holding capacitance;
• a gain control circuit which through a second switch connects an additional gain capacitance in parallel with the charge-holding capacitance, whereby a forward voltage gain is achieved;
• a delay chain comprising bucket-brigade stages in which charge is passed through switches from one capacitive stage to another, thereby delaying the incoming analog signal before it is output from the delay chain;
• wherein said sample and hold circuit, gain control circuit, and delay chain are part of a first bucket-brigade device (BBD);
• and
• an attenuation coupling network which is connected to the output of said first BBD for matching the output offset of said first BBD to the input bias requirement of a subsequent BBD;
• wherein the gain control circuit in a BBD acts in cooperation with the attenuation coupling network to allow cascading sequential BBD devices without the need of a reconstruction filter, or DC blocking, or biasing circuits between each sequential BBD, which in combination provide an extended analog discrete-time delay.

A method of providing a discrete-time delay in an analog signal, comprising:

• sampling, at a first bucket-brigade device (BBD) delay stage, an incoming analog signal to store and hold a charge associated with the incoming analog signal, on a charge holding capacitance;
• switching in additional capacitance to create a forward voltage gain in storing and holding the charge;
• sequentially delaying passing of the charge between bucket-brigade stages of a delay chain in said first BBD delay stage, starting from said charge holding capacitance, in which charge is passed from one capacitive stage to another, incurring a delay of a representation of the incoming analog signal before it is output from the delay chain;
• and
• inserting an attenuation coupling to the end of the delay chain which matches the output offset of the forward voltage gain of this first BBD delay stage, with the input bias requirement of a subsequent BBD delay stage to achieve an extended analog discrete-time delay.