Common adjustment circuit
AssigneeSocionext Inc.
InventorRyuji Nakajima
Life of this patent
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Abstract
A common adjustment circuit includes: a first comparator comparing a reference voltage with a voltage between a first transistor and a first resistance and outputting the comparison result; a current mirror circuit including a second transistor allowing an input current to flow through it and a third transistor allowing an output current to flow through it; a replica circuit imitating a differential amplifier; and a second comparator connected to a connection node between the third transistor and a second resistance at one of its inputs and to a replica output node of the replica circuit at the other input, to compare the two inputs and output a bias voltage.
Claims7
A common adjustment circuit configured to output a first bias voltage to be applied to a gate of an output load transistor of a differential amplifier, comprising:
- a first comparator connected to a reference voltage at one of its inputs and to a first node at the other input, comparing the two inputs and outputting a comparison result;
- a first transistor connected to an output of the first comparator at its gate, to the first node at its source, and to a second node at its drain;
- a first resistance connected to the first node at one of its terminals and to a first power supply at the other terminal;
- a current mirror circuit including a second transistor connected to the second node at its gate and drain and allowing an input current to flow through it, and a third transistor connected to the second node at its gate and allowing an output current to flow through it;
- a second resistance connected to a source of the third transistor at one of its terminals via a third node;
- a second comparator connected to the third node at one of its inputs and to a fourth node at the other input, comparing the two inputs and outputting the first bias voltage;
- and
- a replica circuit including a replica transistor corresponding to the output load transistor of the differential amplifier, a gate of the replica transistor being connected to an output of the second comparator, a replica output node corresponding to an output node of the differential amplifier being connected to the fourth node.
A common adjustment circuit configured to output a bias voltage to be applied to a gate of an output load transistor of a differential amplifier, comprising:
- a first comparator connected to a reference voltage at one of its inputs and to a first node at the other input, comparing the two inputs and outputting a comparison result;
- a first transistor connected to an output of the first comparator at its gate, to the first node at its drain, and to a second node at its source;
- a first resistance connected to the first node at one of its terminals and to a first power supply at the other terminal;
- a second resistance connected to a third node at one of its terminals and to a second power supply different in potential from the first power supply at the other terminal;
- a second comparator connected to the third node at one of its inputs and to a fourth node at the other input, comparing the two inputs and outputting the bias voltage;
- and
- a replica circuit including a replica transistor corresponding to the output load transistor of the differential amplifier, a gate of the replica transistor being connected to an output of the second comparator, a replica output node corresponding to an output node of the differential amplifier being connected to the fourth node.
Dependencies are inferred from the claim text.